公开(公告)号：US12154860B2

公开(公告)日：2024-11-26

申请号：US17348989

申请日：2021-06-16

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Zhongli Ji ,  Ning Ye ,  Chin-Tien Chiu ,  Fen Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method of forming a semiconductor device includes forming vertical contact fingers in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the substrate so that the flexible side portions of the substrate including the contact fingers fold vertically upward to fit within the mold.

公开(公告)号：US11908495B2

公开(公告)日：2024-02-20

申请号：US17725764

申请日：2022-04-21

Applicant: Western Digital Technologies, Inc.

Inventor： Bo Yang ,  Yuhang Yang ,  Ning Ye

IPC: G11B33/14 ,  G11B33/12

CPC classification number: G11B33/1406 ,  G11B33/124 ,  G11B2220/2516

Abstract: Disclosed herein is an electronic device that includes a pedestal that extends from a mounting surface of a base of the electronic device. The electronic device also includes a thermal interface material that is interposed between an interface surface of the pedestal and a data processing component, is in direct contact with the data processing component, and is in direct contact with a first portion and a second portion of the interface surface. The first portion of the interface surface of the pedestal has a first height, relative to the mounting surface of the base, and the second portion of the interface surface of the pedestal has a second height, relative to the mounting surface of the base and different than the first height.

公开(公告)号：US20210384099A1

公开(公告)日：2021-12-09

申请号：US16894068

申请日：2020-06-05

Applicant: Western Digital Technologies, Inc.

Inventor： Bo Yang ,  Chun Sean Lau ,  Ning Ye ,  Shrikar Bhagath

IPC: H01L23/367 ,  H01L23/42

Abstract: A packaged semiconductor device includes a substrate, a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure. The enclosure includes a cover portion having a convexly curved surface configured to apply a pressure to the thermal interface material. The pressure may be substantially uniform over the area of the thermal interface material, or may be higher at a center of the thermal interface material than at a periphery of the thermal interface material.

公开(公告)号：US20200006184A1

公开(公告)日：2020-01-02

申请号：US16277180

申请日：2019-02-15

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Yangming Liu ,  Ning Ye ,  Chin-Tien Chiu

IPC: H01L23/32 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device is disclosed having reinforced supports at corners of the device. The semiconductor device may include solder balls on a lower surface of the device for soldering the device onto a printed circuit board. In one example, the solder balls at the corners of the semiconductor device may be replaced by support billets having more mass and more contact area between the semiconductor device and the PCB. In a further example, screws may be provided at the corners of the device (instead of the corner solder balls or in addition to the corner solder balls). These screws may be placed through the corners of the semiconductor device and into the printed circuit board.

公开(公告)号：US10090014B1

公开(公告)日：2018-10-02

申请号：US15813332

申请日：2017-11-15

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Antony Ajan ,  Kumar Srinivasan ,  Ning Ye

IPC: G11B5/66 ,  G11B5/84 ,  G11B11/105 ,  G11B5/127 ,  G11B5/65 ,  G11B5/00

Abstract: A magnetic recording medium for heat assisted magnetic recording (HAMR) including in ascending vertical sequence: (i) a substrate; (ii) a first amorphous layer, a first seed layer, or a combination thereof; (iii) a heat sink layer comprising hexagonal boron-nitride grains; (iv) an optional second amorphous layer; (v) an optional second seed layer; (vi) a magnetic recording layer; (vii) an optional capping layer; and (viii) an optional overcoat layer; wherein: the magnetic recording medium has a substrate plane and a basal plane perpendicular to the substrate plane; the heat sink layer is anisotropic and has an a-axis thermal conductivity in the basal plane and a c-axis thermal conductivity in the substrate plane, wherein the a-axis thermal conductivity is greater than the c-axis thermal conductivity; and the hexagonal boron-nitride grains have an average size of at least about 10 nm in the substrate plane. Also, provided is a method of manufacturing the magnetic recording medium for HAMR.

公开(公告)号：US20240413573A1

公开(公告)日：2024-12-12

申请号：US18362157

申请日：2023-07-31

Applicant: Western Digital Technologies, Inc.

Inventor： Shiqiang Sun ,  Lihwa Fong ,  Ning Ye

IPC: H01R13/627 ,  H01G2/06 ,  H01G9/02 ,  H01G9/08

Abstract: A snap fit bracket for an electrolytic capacitor is vertically mounted within an opening defined by a substrate. The bracket includes four sidewalls that form a perimeter. A first flange extends from one sidewall and forms a first ledge that sits on a top surface of the substrate when the bracket is mounted within the opening defined by the substrate. A second flange extends from another sidewall and forms a second ledge that sits on the top surface of the substrate when the bracket is mounted within the opening defined by the substrate. A fastener extends from two or more of the sidewalls. A top surface of each fastener contacts a bottom surface of the substrate when the bracket is mounted within the opening defined by the substrate. After vertically mounting the bracket within the substrate, the capacitor disposed within the bracket is horizontally mounted with respect to the PCB.

公开(公告)号：US12013749B2

公开(公告)日：2024-06-18

申请号：US17853510

申请日：2022-06-29

Applicant: Western Digital Technologies, Inc.

Inventor： Hedan Zhang ,  Chaolun Zheng ,  Ning Ye ,  Bret Dee Winkler ,  Yanjun Xia ,  Wei Wu

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/076 ,  G06F11/3037 ,  G06F11/3058 ,  G06F2201/81

Abstract: Methods and apparatus for detecting a failed temperature sensor within a data storage device and for mitigating the loss of the sensor are provided. One such data storage device includes a non-volatile memory (NVM), a set of temperature sensors, and a processor coupled to the NVM and the temperature sensors. The processor is configured to detect failure of one of the temperature sensors and obtain temperature data from the other temperature sensors. The processor is further configured to estimate, based on the obtained temperature data, the temperature at the failed sensor, and then control at least one function of the data storage device based on the estimated temperature, such as controlling entry into a Read Only mode. In some examples, the processor estimates the temperature at the failed sensor or at various virtual sensor locations using pre-determined formulas having offsets and coefficients determined during an initial machine learning calibration procedure.

公开(公告)号：US20230402361A1

公开(公告)日：2023-12-14

申请号：US17840322

申请日：2022-06-14

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Shenghua Huang ,  Binbin Zheng ,  Shaopeng Dong ,  Songtao Lu ,  Rui Guo ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  G06K19/077 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/12 ,  H01L23/3107 ,  H01L25/0657 ,  G06K19/07732 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2924/3512 ,  H01L2924/1511 ,  H01L2224/48135

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.

公开(公告)号：US20230170312A1

公开(公告)日：2023-06-01

申请号：US17536800

申请日：2021-11-29

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Yangming Liu ,  Shenghua Huang ,  Bo Yang ,  Ning Ye ,  Cong Zhang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/552

CPC classification number: H01L23/562 ,  H01L24/48 ,  H01L25/0657 ,  H01L23/552 ,  H01L25/0652 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/3511

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.

公开(公告)号：US20240249950A1

公开(公告)日：2024-07-25

申请号：US18449452

申请日：2023-08-14

Applicant: Western Digital Technologies, Inc.

Inventor： Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L21/3065 ,  H01L21/82 ,  H01L23/00

CPC classification number: H01L21/3065 ,  H01L21/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2924/20641

Abstract: Approaches directed at increasing the production yield of integrated circuits including layers of low-k dielectrics. One example provides a flip-chip assembly including a semiconductor chip attached to a substrate using pillars or bumps. The semiconductor chip has a thickness profile such that the chip is thinner near the corners than in middle portions. The thinner corner portions beneficially alleviate chip-integrity issues related to the stresses generated during the solder reflow operation while the thicker middle portions beneficially alleviate chip-integrity issues related to the stresses generated during the chip or die pick-up operation. Due to the alleviation of both types of chip-integrity issues, the number of instances in which the low-k dielectrics crack during the corresponding assembly operations is significantly reduced, thereby beneficially increasing the manufacturing yield.