公开(公告)号：US11961778B2

公开(公告)日：2024-04-16

申请号：US17486322

申请日：2021-09-27

Applicant: Western Digital Technologies, Inc.

Inventor： Shenghua Huang ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48225 ,  H01L2924/3862

Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.

公开(公告)号：US11978713B2

公开(公告)日：2024-05-07

申请号：US17750047

申请日：2022-05-20

Applicant: Western Digital Technologies, Inc.

Inventor： Shenghua Huang ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/01029

Abstract: The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.

公开(公告)号：US20200006212A1

公开(公告)日：2020-01-02

申请号：US16277244

申请日：2019-02-15

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Rui Guo ,  Songtao Lu ,  Shenghua Huang ,  Ting Liu ,  Chin-Tien Chiu

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

Abstract: A substrate is disclosed having a stress relief layer. The stress relief layer may be applied to a dielectric core of the substrate, beneath a conductive layer in which electrical traces and contact pads are formed. The substrate including the stress relief layer may be incorporated into a semiconductor product which may, for example, be mounted on a host printed circuit board using solder balls on a surface of the substrate. The stress relief layer helps dissipate stresses within the substrate and improves the board level reliability.

公开(公告)号：US12033958B2

公开(公告)日：2024-07-09

申请号：US17536800

申请日：2021-11-29

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Yangming Liu ,  Shenghua Huang ,  Bo Yang ,  Ning Ye ,  Cong Zhang

IPC: H01L23/00 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/552 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/3511

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.

公开(公告)号：US12027497B2

公开(公告)日：2024-07-02

申请号：US17649614

申请日：2022-02-01

Applicant: Western Digital Technologies, Inc.

Inventor： Haiyue Shen ,  Fen Yu ,  Hope Chiu ,  Donghua Wu ,  Hua Tan ,  Xinyu Wang ,  Shenghua Huang

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L2224/48147 ,  H01L2224/48225 ,  H01L2225/06562 ,  H01L2924/1438

Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.

公开(公告)号：US20230395446A1

公开(公告)日：2023-12-07

申请号：US17829719

申请日：2022-06-01

Applicant: Western Digital Technologies, Inc.

Inventor： Yangming Liu ,  Shenghua Huang ,  Bo Yang ,  Ning Ye

IPC: H01L23/24 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/24 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/37001 ,  H01L2924/1438 ,  H01L2224/48148 ,  H01L2224/48229 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06593

Abstract: A semiconductor device including one or more support structures for supporting a semiconductor-die stack having a region that overhangs a substrate. In an example embodiment, the support structures may be implemented using suitably shaped pieces of relatively thick round or ribbon wire attached to metal pads on the substrate. During the encapsulation operation, the one or more support structures may counteract a bending force applied to the semiconductor-die stack by a flow of the molding compound. At least some embodiments may beneficially be used, e.g., to enable high-yield fabrication of devices having sixteen or more stacked memory dies.

公开(公告)号：US20230101826A1

公开(公告)日：2023-03-30

申请号：US17486322

申请日：2021-09-27

Applicant: Western Digital Technologies, Inc.

Inventor： Shenghua Huang ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L23/29

Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.

公开(公告)号：US20230402361A1

公开(公告)日：2023-12-14

申请号：US17840322

申请日：2022-06-14

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Shenghua Huang ,  Binbin Zheng ,  Shaopeng Dong ,  Songtao Lu ,  Rui Guo ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  G06K19/077 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/12 ,  H01L23/3107 ,  H01L25/0657 ,  G06K19/07732 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2924/3512 ,  H01L2924/1511 ,  H01L2224/48135

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.

公开(公告)号：US20230246000A1

公开(公告)日：2023-08-03

申请号：US17649614

申请日：2022-02-01

Applicant: Western Digital Technologies, Inc.

Inventor： Haiyue Shen ,  Fen Yu ,  Hope Chiu ,  Donghua Wu ,  Hua Tan ,  Xinyu Wang ,  Shenghua Huang

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L2224/48147 ,  H01L2224/48225 ,  H01L2225/06562 ,  H01L2924/1438

Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.

公开(公告)号：US20230170312A1

公开(公告)日：2023-06-01

申请号：US17536800

申请日：2021-11-29

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Yangming Liu ,  Shenghua Huang ,  Bo Yang ,  Ning Ye ,  Cong Zhang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/552

CPC classification number: H01L23/562 ,  H01L24/48 ,  H01L25/0657 ,  H01L23/552 ,  H01L25/0652 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/3511

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.