公开(公告)号：US20230066185A1

公开(公告)日：2023-03-02

申请号：US17411770

申请日：2021-08-25

Applicant: Western Digital Technologies, Inc.

Inventor： Rohith Radhakrishnan ,  Alvin Capili Gomez ,  Aashish Sangoi

IPC: G06F11/14 ,  G06F11/30 ,  G06F11/34 ,  G06F1/28

Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of arrays, a number of power regulators, and a controller coupled to the non-volatile memory device. The arrays include a number of memory devices. A first array is determined to be in a non-responsive condition and a power regulator supplying power to the first array is instructed to cycle power to the first array. After the power to the first array has been cycled, a determination is made as to whether the first array is in a responsive condition.

公开(公告)号：US20240264764A1

公开(公告)日：2024-08-08

申请号：US18361537

申请日：2023-07-28

Applicant: Western Digital Technologies, Inc.

Inventor： Rohith Radhakrishnan ,  Alvin Gomez

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0679

Abstract: Devices and techniques are disclosed wherein a data storage device (DSD) generates ranking information corresponding to user data stored at a non-volatile memory of the DSD. The ranking information can be used by the DSD to form a frequently used files list, which can be read by a host system upon initialization with the host system and displayed to a user at the host system.

公开(公告)号：US11782791B2

公开(公告)日：2023-10-10

申请号：US17411770

申请日：2021-08-25

Applicant: Western Digital Technologies, Inc.

Inventor： Rohith Radhakrishnan ,  Alvin Capili Gomez ,  Aashish Sangoi

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/30 ,  G06F11/34 ,  G06F1/28

CPC classification number: G06F11/1441 ,  G06F1/28 ,  G06F11/3034 ,  G06F11/3062 ,  G06F11/3495 ,  G06F2201/805

Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of arrays, a number of power regulators, and a controller coupled to the non-volatile memory device. The arrays include a number of memory devices. A first array is determined to be in a non-responsive condition and a power regulator supplying power to the first array is instructed to cycle power to the first array. After the power to the first array has been cycled, a determination is made as to whether the first array is in a responsive condition.