公开(公告)号：US12107162B2

公开(公告)日：2024-10-01

申请号：US17132293

申请日：2020-12-23

Applicant: Winbond Electronics Corp.

Inventor： Hung-Yu Wei ,  Pei-Hsiu Peng ,  Kai Jen

IPC: H01L29/78 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088

CPC classification number: H01L29/7831 ,  H01L21/77 ,  H01L21/823431 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/41791

Abstract: A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench.

公开(公告)号：US11495605B2

公开(公告)日：2022-11-08

申请号：US17121765

申请日：2020-12-15

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L21/70 ,  H01L27/108

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

公开(公告)号：US11367787B2

公开(公告)日：2022-06-21

申请号：US16681704

申请日：2019-11-12

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang ,  Kai Jen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L27/108 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first channel layer, a first barrier layer, a gate electrode and an insulating structure. The substrate has a recess, and the first channel layer, the first barrier layer, the gate electrode and the insulating structure are disposed in the recess. The first channel layer covers a surface of the recess. The first barrier layer is disposed on a surface of the first channel layer. A surface of a bottom portion of the first barrier layer is covered by the gate electrode, and a top surface of the gate electrode is lower than a topmost surface of the substrate. Surfaces of the gate electrode and a top portion of the first barrier layer are covered by the insulating structure.

公开(公告)号：US20220068930A1

公开(公告)日：2022-03-03

申请号：US17388033

申请日：2021-07-29

Applicant: Winbond Electronics Corp.

Inventor： Te-Hsuan Peng ,  Kai Jen

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311

Abstract: A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

公开(公告)号：US11101179B2

公开(公告)日：2021-08-24

申请号：US16508875

申请日：2019-07-11

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Li-Ting Wang ,  Yi-Hao Chien

IPC: H01L21/8234 ,  H01L27/108 ,  H01L21/768

Abstract: A semiconductor structure includes a semiconductor substrate, a gate stack disposed over the semiconductor substrate, a first oxide spacer disposed along a sidewall of the gate stack, a protection portion disposed over the first oxide spacer, and an interlayer dielectric layer disposed over the semiconductor substrate. The first oxide spacer and the protection portion are disposed between the gate stack and the interlayer dielectric layer.

公开(公告)号：US12193221B2

公开(公告)日：2025-01-07

申请号：US17340507

申请日：2021-06-07

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Kai Jen ,  Yu-Po Wang

IPC: H10B12/00

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

公开(公告)号：US12020945B2

公开(公告)日：2024-06-25

申请号：US17365203

申请日：2021-07-01

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Kai Jen ,  Hsiang-Po Liu

IPC: H01L21/311 ,  H10B12/00

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H10B12/01

Abstract: A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.

公开(公告)号：US11923449B2

公开(公告)日：2024-03-05

申请号：US17739210

申请日：2022-05-09

Applicant: Winbond Electronics Corp.

Inventor： Hao-Chuan Chang ,  Kai Jen

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H10B12/00

CPC classification number: H01L29/7789 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H10B12/053 ,  H10B12/34

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.

公开(公告)号：US20220068939A1

公开(公告)日：2022-03-03

申请号：US17121765

申请日：2020-12-15

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L27/108

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

公开(公告)号：US20220028866A1

公开(公告)日：2022-01-27

申请号：US17498765

申请日：2021-10-12

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

IPC: H01L27/108 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.