公开(公告)号：US20210134810A1

公开(公告)日：2021-05-06

申请号：US16671118

申请日：2019-10-31

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Tzu-Ming Ou Yang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L23/58

Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.

公开(公告)号：US10985262B2

公开(公告)日：2021-04-20

申请号：US16168847

申请日：2018-10-24

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Tzu-Ming Ou Yang ,  Shu-Ming Li ,  Tetsuharu Kurokawa

IPC: H01L21/762 ,  H01L21/308 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/70 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L27/10

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.

公开(公告)号：US20250167124A1

公开(公告)日：2025-05-22

申请号：US18657791

申请日：2024-05-08

Applicant: Winbond Electronics Corp.

Inventor： Meng-Wei Kao ,  Keng-Ping Lin ,  Tzu-Ming Ou Yang ,  Shu-Ming Li

IPC: H01L23/535 ,  H10B12/00

Abstract: A semiconductor structure includes a substrate, stack structures, first spacers, a contact, and second spacers. The stack structures are located on the substrate and separated from each other. The stack structures include a bit line stack structure and a conductive line stack structure. The first spacers are located on sidewalls of the stack structures. Each of the first spacers includes an oxide layer. The contact is located on the substrate between two adjacent first spacers. The top surface of the oxide layer is not higher than the top surface of the contact. The second spacers are located on the first spacers.

公开(公告)号：US11289493B2

公开(公告)日：2022-03-29

申请号：US16671118

申请日：2019-10-31

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Tzu-Ming Ou Yang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L23/58

Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.

公开(公告)号：US11011525B2

公开(公告)日：2021-05-18

申请号：US16554643

申请日：2019-08-29

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Tetsuharu Kurokawa ,  Tzu-Ming Ou Yang ,  Shu-Ming Li

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/31 ,  H01L21/308 ,  H01L21/76 ,  H01L27/108 ,  H01L21/761 ,  H01L29/06

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

公开(公告)号：US20240334685A1

公开(公告)日：2024-10-03

申请号：US18327842

申请日：2023-06-01

Applicant: Winbond Electronics Corp.

Inventor： Te-Hsuan Peng ,  Keng-Ping Lin

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02 ,  H10B12/482 ,  H10B12/485

Abstract: Provided are a dynamic random access memory and a method for manufacturing the same. The DRAM includes: a plurality of word line structures, located in a substrate; a plurality of bit line structures, located above the substrate, crossing over the plurality of word line structures; a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures; and a plurality of first spacers, separating the plurality of node contacts. Each of the plurality of first spacers further comprises: spacer material, filled in a gap between the node contacts that are adjacent; and a first cap layer, embedded in the spacer material.

公开(公告)号：US11610897B2

公开(公告)日：2023-03-21

申请号：US17225113

申请日：2021-04-08

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Tetsuharu Kurokawa ,  Tzu-Ming Ou Yang ,  Shu-Ming Li

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/761 ,  H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

公开(公告)号：US20220352172A1

公开(公告)日：2022-11-03

申请号：US17306874

申请日：2021-05-03

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Shu-Ming Li ,  Tzu-Ming Ou Yang

IPC: H01L27/108

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

公开(公告)号：US20210225850A1

公开(公告)日：2021-07-22

申请号：US17225113

申请日：2021-04-08

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Tetsuharu Kurokawa ,  Tzu-Ming Ou Yang ,  Shu-Ming Li

IPC: H01L27/108 ,  H01L21/761 ,  H01L29/06 ,  H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

公开(公告)号：US12262528B2

公开(公告)日：2025-03-25

申请号：US17973558

申请日：2022-10-26

Applicant: Winbond Electronics Corp.

Inventor： Keng-Ping Lin ,  Shu-Ming Li ,  Tzu-Ming Ou Yang

IPC: H10B12/00

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.