公开(公告)号：US12176440B2

公开(公告)日：2024-12-24

申请号：US17518270

申请日：2021-11-03

Applicant: Winbond Electronics Corp.

Inventor： Shang-Rong Wu ,  Ming-Che Lin ,  Chung-Hsien Liu

IPC: H01L21/764 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method of forming the semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

公开(公告)号：US20220068382A1

公开(公告)日：2022-03-03

申请号：US17458559

申请日：2021-08-27

Applicant: Winbond Electronics Corp.

Inventor： Ming-Che Lin ,  Min-Chih Wei ,  Ping-Kun Wang ,  Yu-Ting Chen ,  Chih-Cheng Fu ,  Chang-Tsung Pai

IPC: G11C13/00

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

公开(公告)号：US20220028454A1

公开(公告)日：2022-01-27

申请号：US17495778

申请日：2021-10-06

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.

公开(公告)号：US11107983B2

公开(公告)日：2021-08-31

申请号：US17060300

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Chih-Cheng Fu ,  Ming-Che Lin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A RRAM array and its manufacturing method are provided. The RRAM array includes a substrate having an array region which has a first region and a second region. The RRAM array includes a bottom electrode layer on the substrate, an oxygen ion reservoir layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion reservoir layer, a resistance switching layer on the diffusion barrier layer, and a top electrode layer on the resistance switching layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.

公开(公告)号：US20210012839A1

公开(公告)日：2021-01-14

申请号：US15930469

申请日：2020-05-13

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.

公开(公告)号：US10770167B1

公开(公告)日：2020-09-08

申请号：US16281063

申请日：2019-02-20

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Chien-Min Wu ,  He-Hsuan Chao ,  Chih-Cheng Fu ,  Shao-Ching Liao

IPC: G11C13/00 ,  G11C29/50 ,  G11C29/02 ,  G11C29/24

Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

公开(公告)号：US20200265914A1

公开(公告)日：2020-08-20

申请号：US16281063

申请日：2019-02-20

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Chien-Min Wu ,  He-Hsuan Chao ,  Chih-Cheng Fu ,  Shao-Ching Liao

IPC: G11C29/50 ,  G11C13/00 ,  G11C29/24 ,  G11C29/02

Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

公开(公告)号：US11758740B2

公开(公告)日：2023-09-12

申请号：US17224152

申请日：2021-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chang-Tsung Pai ,  Chiung-Lin Hsu ,  Yu-Ting Chen ,  Ming-Che Lin ,  Chi-Ching Liu

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10N70/011 ,  H10N70/253 ,  H10N70/8265 ,  H10N70/841

Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.

公开(公告)号：US11620500B2

公开(公告)日：2023-04-04

申请号：US15868392

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Chih-Cheng Fu ,  Ming-Che Lin ,  Yu-Ting Chen ,  Seow-Fong (Dennis) Lim

IPC: G06N3/049 ,  G06N3/08 ,  G11C11/54 ,  G06N3/065 ,  G11C13/00

Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.

公开(公告)号：US20220069209A1

公开(公告)日：2022-03-03

申请号：US17002759

申请日：2020-08-25

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Chia-Wen Cheng ,  He-Hsuan Chao ,  Frederick Chen ,  Chang-Tsung Pai ,  Tzu-Yun Huang ,  Ming-Che Lin

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.