公开(公告)号：US20240179903A1

公开(公告)日：2024-05-30

申请号：US17993997

申请日：2022-11-25

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Wei-Che Chang

IPC: H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

公开(公告)号：US10366995B2

公开(公告)日：2019-07-30

申请号：US15979476

申请日：2018-05-15

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Yoshinori Tanaka

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.

公开(公告)号：US12300612B2

公开(公告)日：2025-05-13

申请号：US17731180

申请日：2022-04-27

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang

IPC: H10B12/00 ,  G11C5/06 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.

公开(公告)号：US11495605B2

公开(公告)日：2022-11-08

申请号：US17121765

申请日：2020-12-15

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L21/70 ,  H01L27/108

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

公开(公告)号：US11335770B2

公开(公告)日：2022-05-17

申请号：US16885286

申请日：2020-05-28

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L27/108

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

公开(公告)号：US20230076269A1

公开(公告)日：2023-03-09

申请号：US17881635

申请日：2022-08-05

Applicant: Winbond Electronics Corp.

Inventor： Ying-Chu Yen ,  Wei-Che Chang

IPC: H01L21/66 ,  H01L27/108 ,  H01L21/67

Abstract: A method and system for monitoring and controlling a semiconductor process are provided. The method includes: forming at least one active region on a substrate; forming a first patterned photoresist layer for defining at least two word lines on the active region after forming the active region; detecting and measuring positions and dimensions of the active region and the first patterned photoresist layer and calculating estimated areas of at least two estimated contact windows in the active region according to a predefined position of at least one bit line; adjusting the predefined position of the at least one bit line according to the estimated areas of the at least two estimated contact windows in the active region; and forming a second patterned photoresist layer on the substrate. The second patterned photoresist layer corresponds to the adjusted predefined position of the at least one bit line.

公开(公告)号：US20190393226A1

公开(公告)日：2019-12-26

申请号：US16197380

申请日：2018-11-21

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/06

Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.

公开(公告)号：US10332572B2

公开(公告)日：2019-06-25

申请号：US16005698

申请日：2018-06-12

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Yoshinori Tanaka

IPC: G11C7/18 ,  H01L27/105 ,  H01L21/027 ,  H01L21/762 ,  G11C5/02 ,  G11C8/14

Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.

公开(公告)号：US20190006369A1

公开(公告)日：2019-01-03

申请号：US15979476

申请日：2018-05-15

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Yoshinori Tanaka

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/10891 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649

Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.

公开(公告)号：US10074654B1

公开(公告)日：2018-09-11

申请号：US15942439

申请日：2018-03-31

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Kazutaka Manabe ,  Noriaki Ikeda ,  Wei-Che Chang

IPC: H01L27/108

CPC classification number: H01L27/10808 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876

Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.