公开(公告)号：US11145617B2

公开(公告)日：2021-10-12

申请号：US16360040

申请日：2019-03-21

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H01L23/14 ,  H01L23/00 ,  H01L25/065 ,  H01R4/2407 ,  H01R12/62 ,  H01L23/498

Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.

公开(公告)号：US10609824B2

公开(公告)日：2020-03-31

申请号：US16660832

申请日：2019-10-23

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/46 ,  B33Y80/00 ,  H05K1/14 ,  H05K1/11 ,  H05K3/12 ,  H05K3/00 ,  H05K1/03 ,  H05K3/40

Abstract: A multi-layer circuit board including a plurality of insulation bumps, a first conductive layer, and a second conductive layer is provided. The plurality of insulation bumps are disposed between a first substrate and a second substrate. A top portion of the plurality of insulation bumps is served as a circuit connection point. The first conductive layer is disposed on the first substrate and connected to the circuit connection point. The second conductive layer is disposed on the second substrate and connected to the circuit connection point.

公开(公告)号：US20180211931A1

公开(公告)日：2018-07-26

申请号：US15867715

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01R4/2407 ,  H01R12/62

CPC classification number: H01L24/50 ,  H01L23/4985 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/13016 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2225/06562 ,  H01L2225/06579 ,  H01R4/2407 ,  H01R12/62

Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.

公开(公告)号：US10297566B2

公开(公告)日：2019-05-21

申请号：US15867715

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H01L23/14 ,  H01L23/00 ,  H01L25/065 ,  H01R4/2407 ,  H01R12/62 ,  H01L23/498

Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.

公开(公告)号：US09991232B2

公开(公告)日：2018-06-05

申请号：US15253823

申请日：2016-08-31

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L24/05 ,  H01L24/09 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2225/06551 ,  H01L2225/06562

Abstract: A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned conductive layer are formed through 3D-printing over a carrier having a cavity. The patterned conductive layer and the solder resist layer extend to the outside of the cavity from the inside of the cavity. One portion of the patterned conductive layer is exposed by the solder resist layer. At least one semiconductor device is mounted on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer.

公开(公告)号：US20180005993A1

公开(公告)日：2018-01-04

申请号：US15253823

申请日：2016-08-31

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L24/05 ,  H01L24/09 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2225/06551 ,  H01L2225/06562

Abstract: A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned conductive layer are formed through 3D-printing over a carrier having a cavity. The patterned conductive layer and the solder resist layer extend to the outside of the cavity from the inside of the cavity. One portion of the patterned conductive layer is exposed by the solder resist layer. At least one semiconductor device is mounted on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer.

公开(公告)号：US20200053884A1

公开(公告)日：2020-02-13

申请号：US16660832

申请日：2019-10-23

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H05K3/46 ,  B33Y80/00 ,  H05K1/14 ,  H05K1/11 ,  H05K3/12 ,  H05K3/00 ,  H05K1/03

Abstract: A multi-layer circuit board including a plurality of insulation bumps, a first conductive layer, and a second conductive layer is provided. The plurality of insulation bumps are disposed between a first substrate and a second substrate. A top portion of the plurality of insulation bumps is served as a circuit connection point. The first conductive layer is disposed on the first substrate and connected to the circuit connection point. The second conductive layer is disposed on the second substrate and connected to the circuit connection point.

公开(公告)号：US10470316B2

公开(公告)日：2019-11-05

申请号：US15808818

申请日：2017-11-09

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen ,  Yi-Der Wu

IPC: B29C41/02 ,  H05K3/46 ,  H05K3/00 ,  H05K3/40 ,  B29C64/30 ,  B33Y80/00 ,  B29C64/129 ,  B29C64/386 ,  B29C64/124 ,  B29C64/112 ,  B29C64/393 ,  H05K3/12 ,  B29C64/118 ,  B29L31/34 ,  B33Y10/00

Abstract: A manufacturing method of a circuit board includes: performing a first printing process to form a first insulating layer having a first circuit depressed pattern; performing a second printing process to form a first circuit layer in the first circuit depressed pattern; checking whether a real position of the first circuit layer is diverged from a predetermined position; determining whether the shift level of the position of the first circuit layer is more than a predetermined level; performing the first printing process to form the second insulating layer, wherein when the shift level is more than the predetermined level and the thickness of a second insulating layer to be formed on the first insulating layer is not greater than a tolerance thickness, the second insulating layer has a hole at least partially overlapping the real position; and performing the second printing process to form a conductive plug in the hole.

公开(公告)号：US10096567B2

公开(公告)日：2018-10-09

申请号：US15922900

申请日：2018-03-15

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen

IPC: H01L23/00 ,  H01L23/31

Abstract: A package substrate including a carrier, a first patterned conductive layer, a second patterned conductive layer and a 3D-printing conductive wire is provided. The carrier has a first surface, a second surface and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface. The second patterned conductive layer is disposed on the second surface. The 3D-printing conductive wire is disposed on the third surface and connected between the first patterned conductive layer and the second patterned conductive layer.

公开(公告)号：US20180139854A1

公开(公告)日：2018-05-17

申请号：US15808818

申请日：2017-11-09

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ming Chen ,  Yi-Der Wu

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/12 ,  H05K3/40 ,  B29C64/129 ,  B29C64/30 ,  B33Y10/00 ,  B33Y80/00

Abstract: A manufacturing method of a circuit board includes: performing a first printing process to form a first insulating layer having a first circuit depressed pattern; performing a second printing process to form a first circuit layer in the first circuit depressed pattern; checking whether a real position of the first circuit layer is diverged from a predetermined position; determining whether the shift level of the position of the first circuit layer is more than a predetermined level; performing the first printing process to form the second insulating layer, wherein when the shift level is more than the predetermined level and the thickness of a second insulating layer to be formed on the first insulating layer is not greater than a tolerance thickness, the second insulating layer has a hole at least partially overlapping the real position; and performing the second printing process to form a conductive plug in the hole.