公开(公告)号：US12148705B2

公开(公告)日：2024-11-19

申请号：US17336214

申请日：2021-06-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/538 ,  H01L23/498 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method for forming a three-dimensional (3D) memory device includes the following operations. First, in a first semiconductor structure, logic process-compatible devices and first bonding contacts are formed conductively connected to the logic process-compatible devices. In a second semiconductor structure, an array of NAND memory cells and second bonding contacts are formed conductively connected to the array of NAND memory cells. A first surface of an interposer structure is bonded to the second semiconductor structure. First interposer contacts disposed at the first surface of the interposer structure are conductively connected to the second bonding contacts. A second surface of the interposer structure is bonded to the first semiconductor structure. Second interposer contacts disposed at the second surface of the interposer structure are conductively connected to the first bonding contacts. The interposer structure is attached to the first semiconductor structure and the second semiconductor structure.

公开(公告)号：US11996389B2

公开(公告)日：2024-05-28

申请号：US17182175

申请日：2021-02-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H10B10/00 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one first semiconductor structure includes a programmable logic device, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one second semiconductor structure includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one die includes the bonded first and second semiconductor structures.

公开(公告)号：US11887954B2

公开(公告)日：2024-01-30

申请号：US17521332

申请日：2021-11-08

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2225/06544

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.

公开(公告)号：US11728236B2

公开(公告)日：2023-08-15

申请号：US17482361

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H10B41/27 ,  H10B41/35 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/3192 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0657 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Embodiments of three-dimensional (3D) memory devices have a blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic devices, a pad-out interconnect layer above the semiconductor layer, and a blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen.

公开(公告)号：US20230253364A1

公开(公告)日：2023-08-10

申请号：US18135453

申请日：2023-04-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524

Abstract: A semiconductor device in a multi-chip package (MCP) includes a controller, at least one non-volatile memory die including an array of non-volatile memory cells and connected to the controller through wire bonding, and at least one volatile memory die including an array of volatile memory cells and connected to the controller through wire bonding. The controller is configured to control operations of the at least one non-volatile memory die and the at least one volatile memory die.

公开(公告)号：US11551753B2

公开(公告)日：2023-01-10

申请号：US17207258

申请日：2021-03-19

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: G11C14/00 ,  G11C16/04 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/108 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L21/50 ,  H01L27/06 ,  H01L27/1157 ,  H01L27/11578

Abstract: Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

公开(公告)号：US11367729B2

公开(公告)日：2022-06-21

申请号：US16669445

申请日：2019-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  H01L27/108

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US11302706B2

公开(公告)日：2022-04-12

申请号：US16565481

申请日：2019-09-09

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L27/11 ,  H01L27/1157 ,  H01L21/50 ,  H01L23/00 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11578

Abstract: Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a unified semiconductor chip includes a first semiconductor structure including one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. The unified semiconductor chip also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The unified semiconductor chip further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20220068941A1

公开(公告)日：2022-03-03

申请号：US17524478

申请日：2021-11-11

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  H01L27/108

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.

公开(公告)号：US20210305259A1

公开(公告)日：2021-09-30

申请号：US17344942

申请日：2021-06-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H01L27/11 ,  H01L21/76 ,  H01L23/00

Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.