公开(公告)号：US20250157900A1

公开(公告)日：2025-05-15

申请号：US18515985

申请日：2023-11-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Hao Zheng ,  Dongyu Fan ,  Peng Chen ,  Zhong Lv ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

Abstract: In certain aspects, a semiconductor packaging structure includes an interposer structure, which includes an interconnect bridge, a device circuit, a set of conductive elements, and a molding layer. The interconnect bridge includes a stack of conductive layers and dielectric layers that are disposed alternately and an interconnect structure formed in the stack and penetrating at least part of the stack to connect to a conductive layer in the stack. The device circuit is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on a periphery of the device circuit. The interconnect structure of the interconnect bridge is connected to at least one conductive element from the set of conductive elements. The molding layer encapsulates the device circuit and the set of conductive elements.

公开(公告)号：US12278209B2

公开(公告)日：2025-04-15

申请号：US17510779

申请日：2021-10-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L25/065 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

公开(公告)号：US12262533B2

公开(公告)日：2025-03-25

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/52 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

公开(公告)号：US12191269B2

公开(公告)日：2025-01-07

申请号：US17483121

申请日：2021-09-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H01L29/76 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

公开(公告)号：US20240431108A1

公开(公告)日：2024-12-26

申请号：US18824568

申请日：2024-09-04

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong Zhang ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B43/27 ,  H10B41/27

Abstract: According to one aspect of the present disclosure, a three-dimensional memory is provided. The three-dimensional memory may include a stack structure comprising a gate layer and a dielectric layer disposed alternately and comprising a plurality of steps. The three-dimensional memory may include an etch stop layer disposed on the plurality of steps. The three-dimensional memory may include a protective layer covering the stack structure and the etch stop layer. The three-dimensional memory may include a plurality of connection pillars. Each of the connection pillars penetrates through the protective layer and the etch stop layer on a corresponding step and is connected with the gate layer of the corresponding step.

公开(公告)号：US20240389331A1

公开(公告)日：2024-11-21

申请号：US18792202

申请日：2024-08-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H10B43/40 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41

Abstract: In certain aspects, a semiconductor device includes a substrate and a first transistor. The first transistor includes a first well in the substrate and having a recess, a recess gate structure including a protrusion structure, and a first source and a first drain spaced apart by the recess gate structure. The protrusion structure extends into the recess of the first well. The recess gate structure includes a first gate dielectric and a first gate electrode on the first gate dielectric.

公开(公告)号：US12136586B2

公开(公告)日：2024-11-05

申请号：US18083339

申请日：2022-12-16

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L23/48 ,  H01L21/48 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

公开(公告)号：US12127393B2

公开(公告)日：2024-10-22

申请号：US17539742

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L29/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B12/33 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/036 ,  H10B12/05 ,  H10B12/482 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441 ,  H01L2924/1444

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

公开(公告)号：US12096631B2

公开(公告)日：2024-09-17

申请号：US17113492

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Zhongwang Sun ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: In a method for fabricating a semiconductor device, an initial stack is formed. The initial stack is formed of sacrificial layers and insulating layers that are alternatingly disposed over a substrate, and includes a first connection region, a first array region, and a second connection region that are disposed sequentially. A first initial staircase is formed in the first connection region and formed in a first group of sacrificial layers and insulating layers. A first top select gate staircase is formed in the second connection region, and formed in a second group of sacrificial layers and insulating layers. An etching process is subsequently performed in the first connection region to shift the first initial staircase toward the substrate along a vertical direction perpendicular to the substrate so as to form a first bottom select gate staircase.

公开(公告)号：US12082407B2

公开(公告)日：2024-09-03

申请号：US17483176

申请日：2021-09-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H10B41/40 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/40 ,  H01L23/481 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/80001

Abstract: A three-dimensional (3D) memory device includes a first substrate, a first semiconductor structure, and a second semiconductor structure. The first semiconductor structure is disposed on the first substrate. The first semiconductor structure includes a second substrate, and a peripheral device disposed over the second substrate, and the peripheral device is formed facing the first substrate. The second semiconductor structure is disposed on the first semiconductor structure. The second semiconductor structure includes a doped semiconductor layer, and a memory array structure disposed between the doped semiconductor layer and the first semiconductor structure.