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    Two-dimensional encounter location detection
    1.
    发明授权
    Two-dimensional encounter location detection 有权

    公开(公告)号：US10536923B2

    公开(公告)日：2020-01-14

    申请号：US16062103

    申请日：2015-12-26

    Applicant: Yi Lin Chen ,  Mi Sun Park ,  Shao-Wen Yang ,  Lei Yang ,  Intel Corporation

    Inventor： Yi Lin Chen ,  Mi Sun Park ,  Shao-Wen Yang ,  Lei Yang

    IPC: G01S5/02 ,  H04W64/00 ,  H04W4/02 ,  H04W4/70 ,  H04W4/029 ,  G01S11/06

    Abstract: Sensors provisioned on a first device detect a movement of the first device corresponding to the first device changing position within an environment. Location information for the first device is updated based on the position change. A plurality of signals are detected, at the first device, from a second device in the environment, determine, and a distance between the first and second devices is determined based on each of the signals. From the signals, another change in position of the first device within the environment is determined and the location information updated for the first device. The movement is detected at the first device at an instance between two of the plurality of signals, and location information for the first device based on the first position change is updated prior to detection of the later of the two signals in the plurality of signals.

    Memory controller and signal synchronizing method thereof
    3.
    发明授权
    Memory controller and signal synchronizing method thereof 有权
    存储器控制器及其信号同步方法

    公开(公告)号：US07890786B2

    公开(公告)日：2011-02-15

    申请号：US11948800

    申请日：2007-11-30

    Applicant: Yi Lin Chen ,  Yi Chih Huang

    Inventor： Yi Lin Chen ,  Yi Chih Huang

    IPC: G06F1/04

    CPC classification number: G06F13/1689

    Abstract: A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

    Abstract translation: 存储器控制器包括用于接收时钟信号并将时钟信号输出到外部存储器的输出缓冲器; 以及用于接收时钟信号并将时钟信号输出到计数电路的副本缓冲器; 其中复制缓冲器和输出缓冲器具有相同的延迟时间，使得由计数电路接收的时钟信号可以与由外部存储器接收的时钟信号同步，因此计数电路可以根据时钟精确地计数到预定时间 信号并输出​​使能信号以启用数据控制信号。 本发明还提供了一种用于存储器控制器的信号同步方法。

    MEMORY CONTROLLER AND SIGNAL SYNCHRONIZING METHOD THEREOF
    4.
    发明申请
    MEMORY CONTROLLER AND SIGNAL SYNCHRONIZING METHOD THEREOF 有权
    内存控制器及其信号同步方法

    公开(公告)号：US20080133959A1

    公开(公告)日：2008-06-05

    申请号：US11948800

    申请日：2007-11-30

    Applicant: Yi Lin Chen ,  Yi Chih Huang

    Inventor： Yi Lin Chen ,  Yi Chih Huang

    IPC: G06F1/06

    CPC classification number: G06F13/1689

    Abstract: A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

    Abstract translation: 存储器控制器包括用于接收时钟信号并将时钟信号输出到外部存储器的输出缓冲器; 以及用于接收时钟信号并将时钟信号输出到计数电路的副本缓冲器; 其中复制缓冲器和输出缓冲器具有相同的延迟时间，使得由计数电路接收的时钟信号可以与由外部存储器接收的时钟信号同步，因此计数电路可以根据时钟精确地计数到预定时间 信号并输出​​使能信号以启用数据控制信号。 本发明还提供了一种用于存储器控制器的信号同步方法。

    Signal sampling apparatus and method for DRAM memory
    6.
    发明授权
    Signal sampling apparatus and method for DRAM memory 有权
    用于DRAM存储器的信号采样装置和方法

    公开(公告)号：US07652936B2

    公开(公告)日：2010-01-26

    申请号：US11675572

    申请日：2007-02-15

    Applicant: Yi Lin Chen

    Inventor： Yi Lin Chen

    IPC: G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C5/00

    CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076

    Abstract: A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.

    Abstract translation: 一种用于DRAM存储器的信号采样装置，包括相位延迟电路，其适于接收数据信号并延迟数据信号预定时间以产生延迟信号; 以及用于根据延迟信号对数据信号进行采样的采样电路。

    TWO-DIMENSIONAL ENCOUNTER LOCATION DETECTION
    7.
    发明申请
    TWO-DIMENSIONAL ENCOUNTER LOCATION DETECTION 审中-公开

    公开(公告)号：US20190007924A1

    公开(公告)日：2019-01-03

    申请号：US16062103

    申请日：2015-12-26

    Applicant: Yi Lin CHEN ,  Mi Sun PARK ,  Shao-Wen YANG ,  Lei YANG ,  Intel Corporation

    Inventor： Yi Lin Chen ,  Mi Sun Park ,  Shao-Wen Yang ,  Lei Yang

    IPC: H04W64/00 ,  H04W4/02 ,  H04W4/029 ,  H04W4/70

    CPC classification number: H04W64/003 ,  G01S5/02 ,  G01S11/06 ,  H04W4/027 ,  H04W4/029 ,  H04W4/70

    Abstract: Sensors provisioned on a first device detect a movement of the first device corresponding to the first device changing position within an environment. Location information for the first device is updated based on the position change. A plurality of signals are detected, at the first device, from a second device in the environment, determine, and a distance between the first and second devices is determined based on each of the signals. From the signals, another change in position of the first device within the environment is determined and the location information updated for the first device. The movement is detected at the first device at an instance between two of the plurality of signals, and location information for the first device based on the first position change is updated prior to detection of the later of the two signals in the plurality of signals.

    Circuit and method for calibrating data control signal
    9.
    发明授权
    Circuit and method for calibrating data control signal 有权
    用于校准数据控制信号的电路和方法

    公开(公告)号：US07697371B2

    公开(公告)日：2010-04-13

    申请号：US11948745

    申请日：2007-11-30

    Applicant: Yi Lin Chen ,  Cheng Hsin Chang

    Inventor： Yi Lin Chen ,  Cheng Hsin Chang

    IPC: G11C8/18

    CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

    Abstract: A circuit for calibrating a data control signal includes a time-delay compensation circuit and a voltage-control delay circuit. The time-delay compensation circuit receives two complementary signals and a direct current voltage which has two voltage cross points with the two complementary signals respectively, and outputs a control voltage according to a time difference between the two voltage cross points. The voltage-control delay circuit delays a data control signal for a predetermined time according to the control voltage, thereby eliminating signal skew between the data control signal and a data signal.

    Abstract translation: 用于校准数据控制信号的电路包括时间延迟补偿电路和电压控制延迟电路。 时间延迟补偿电路分别接收两个互补信号和一个具有两个互补信号的两个电压交叉点的直流电压，并根据两个电压交叉点之间的时间差输出控制电压。 电压控制延迟电路根据控制电压使数据控制信号延迟预定时间，从而消除数据控制信号和数据信号之间的信号偏移。

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