公开(公告)号：US20080089153A1

公开(公告)日：2008-04-17

申请号：US11878087

申请日：2007-07-20

Applicant: Young-yong Byun ,  Hi-choon Lee

Inventor： Young-yong Byun ,  Hi-choon Lee

IPC: G11C29/04

CPC classification number: G11C29/40

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

Abstract translation: 提供一种半导体存储器件及其方法。 示例性半导体存储器件可以包括多个比较器，其从多个子阵列块中的每一个接收输出数据信号，比较来自多个子阵列块中的每一个的输出数据信号并输出​​多个比较结果信号;以及 测试电路分别从多个比较器接收多个比较结果信号，该测试电路被配置为在给定的数据输入/输出焊盘上选择性地输出多个比较结果信号中给定的一个中的一个，以及获得的给定信号 通过响应于选择信号对给定数据输入/输出焊盘上的多个比较结果信号中的至少两个进行逻辑运算。

公开(公告)号：US07656207B2

公开(公告)日：2010-02-02

申请号：US12009080

申请日：2008-01-16

Applicant: Young-yong Byun

Inventor： Young-yong Byun

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/085 ,  H03L7/10

Abstract: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

Abstract translation: 提供一种具有适应于外部时钟信号的频带的粗略锁定时间的DLL电路和具有该DLL电路的半导体存储器件。 DLL电路包括延迟电路，复制电路和相位检测器。 相位检测器产生由延迟电路使用的第一比较信号，以以第一单元延迟时间为单位延迟外部时钟信号或延迟电路使用的第二比较信号，以以第二单元延迟为单位延迟外部时钟信号 时间。 DLL电路将外部时钟信号延迟自适应外部时钟信号的频带的单元延迟时间，从而可以对整个频带执行准确和快速的粗略锁定操作。

公开(公告)号：US20080180149A1

公开(公告)日：2008-07-31

申请号：US12009080

申请日：2008-01-16

Applicant: Young-yong Byun

Inventor： Young-yong Byun

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/085 ,  H03L7/10

Abstract: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

Abstract translation: 提供一种具有适应于外部时钟信号的频带的粗略锁定时间的DLL电路和具有该DLL电路的半导体存储器件。 DLL电路包括延迟电路，复制电路和相位检测器。 相位检测器产生由延迟电路使用的第一比较信号，以以第一单元延迟时间为单位延迟外部时钟信号或延迟电路使用的第二比较信号，以以第二单元延迟为单位延迟外部时钟信号 时间。 DLL电路将外部时钟信号延迟自适应外部时钟信号的频带的单元延迟时间，从而可以对整个频带执行准确和快速的粗略锁定操作。

公开(公告)号：US08310859B2

公开(公告)日：2012-11-13

申请号：US12570159

申请日：2009-09-30

Applicant: Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

Inventor： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

IPC: G11C11/24

CPC classification number: G11C8/14 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract translation: 半导体存储器件包括多个存储单元块，它们包括具有位线的第一存储单元块，边沿读出放大器块，其包括耦合到第一存储单元块的位线的一部分的边沿读出放大器，以及平衡电容器单元 耦合到边缘读出放大器。

公开(公告)号：US07755958B2

公开(公告)日：2010-07-13

申请号：US11878087

申请日：2007-07-20

Applicant: Young-yong Byun ,  Hi-choon Lee

Inventor： Young-yong Byun ,  Hi-choon Lee

IPC: G11C29/00

CPC classification number: G11C29/40

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

Abstract translation: 提供一种半导体存储器件及其方法。 示例性半导体存储器件可以包括多个比较器，其从多个子阵列块中的每一个接收输出数据信号，比较来自多个子阵列块中的每一个的输出数据信号并输出​​多个比较结果信号;以及 测试电路分别从多个比较器接收多个比较结果信号，该测试电路被配置为在给定的数据输入/输出焊盘上选择性地输出多个比较结果信号中给定的一个中的一个，以及获得的给定信号 通过响应于选择信号对给定数据输入/输出焊盘上的多个比较结果信号中的至少两个进行逻辑运算。