公开(公告)号：US08570480B2

公开(公告)日：2013-10-29

申请号：US12410475

申请日：2009-03-25

Applicant: Yi-Chen Chiang ,  Chih-Hung Shih ,  Maw-Song Chen ,  Tzu-Wei Ho ,  Ching-Huan Lin ,  Yu-Hsuan Li ,  Yao-Jen Hsieh ,  Ya-Ting Hsu ,  Chi-Mao Hung ,  Ken-Ming Chen ,  Yu-Cheng Chen

Inventor： Yi-Chen Chiang ,  Chih-Hung Shih ,  Maw-Song Chen ,  Tzu-Wei Ho ,  Ching-Huan Lin ,  Yu-Hsuan Li ,  Yao-Jen Hsieh ,  Ya-Ting Hsu ,  Chi-Mao Hung ,  Ken-Ming Chen ,  Yu-Cheng Chen

IPC: G02F1/1345 ,  G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3648 ,  G02F1/1345 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0232 ,  G09G2310/0278

Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Abstract translation: 公开了一种具有纤细边框结构的显示装置。 显示装置包括基板，多条数据线，多条栅极线，多条辅助栅极线和驱动模块。 基板包括显示区域和边界区域。 数据线，栅极线和辅助栅极线设置在显示区域中。 驱动模块设置在边界区域。 栅极线与数据线垂直交叉。 辅助栅极线与数据线并联。 每个辅助栅极线电连接到一个对应的栅极线。 数据和辅助栅极线基于交错布置电连接到驱动模块。 另外公开了一种驱动方法，用于通过辅助栅极线将由驱动模块提供的栅极信号传送到栅极线。

公开(公告)号：US08553193B2

公开(公告)日：2013-10-08

申请号：US12909831

申请日：2010-10-22

Applicant: Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen ,  Tsan-Chun Wang

Inventor： Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen ,  Tsan-Chun Wang

IPC: G02F1/1343

CPC classification number: G02F1/13624 ,  G02F2001/13606

Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.

Abstract translation: 像素结构包括第一和第二扫描线，数据线，覆盖第一和第二扫描线的第一绝缘层和数据线的一部分并具有凹部，覆盖第一绝缘层的第二绝缘层， 覆盖数据线和凹部的电容器电极线，电容器电极线上的第三绝缘层，与第二扫描线和数据线电连接的第一有源器件，与第一有源器件电连接的第二有源器件， 第一扫描线以及分别电连接到第一和第二有源器件的第一和第二像素电极。 数据线和第一和第二扫描线的部分在同一层中。 凹槽位于数据线部分的两侧。

公开(公告)号：US08541750B2

公开(公告)日：2013-09-24

申请号：US12553982

申请日：2009-09-03

Applicant: Yu-Cheng Chen ,  An-Thung Cho ,  Ching-Sang Chuang ,  Chia-Tien Peng

Inventor： Yu-Cheng Chen ,  An-Thung Cho ,  Ching-Sang Chuang ,  Chia-Tien Peng

IPC: G01T1/20

CPC classification number: H01L31/085

Abstract: A structure of X-ray detector includes a Si-rich dielectric material for serving as a photo-sensing layer to increase light sensitivity. The fabrication method of the X-ray detector including the Si-rich dielectric material needs less photolithography-etching processes, so as to reduce the total thickness of thin film layers and decrease process steps and cost.

Abstract translation: X射线检测器的结构包括用作光敏层的富Si介电材料以增加光敏度。 包含富Si介电材料的X射线检测器的制造方法需要较少的光刻蚀刻工艺，以减少薄膜层的总厚度并降低工艺步骤和成本。

公开(公告)号：US08279365B2

公开(公告)日：2012-10-02

申请号：US12814503

申请日：2010-06-14

Applicant: Tsan-Chun Wang ,  Yu-Cheng Chen

Inventor： Tsan-Chun Wang ,  Yu-Cheng Chen

IPC: G02F1/1343 ,  G02F1/136

CPC classification number: G02F1/1368 ,  G02F1/13624

Abstract: An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd1. In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd2, the gate-to-drain capacitances of the other active devices are Cgd1, and Cgd1≠Cgd2.

Abstract translation: 有源器件阵列衬底包括衬底，设置在衬底上的扫描线，与扫描线相交的数据线，扫描信号传输线和像素单元。 扫描信号传输线与扫描线相交。 每条扫描信号传输线通过一个节点连接一条扫描线。 像素单元电连接对应的数据线和相应的扫描线，并且包括有源器件和像素电极。 有源器件具有栅极，源极和漏极。 像素电极电连接漏极。 在与节点不相邻的像素单元中，每个有源器件的栅极 - 漏极电容为Cgd1。 在与节点相邻的像素单元中，一些有源器件的栅极至漏极电容为Cgd2，其他有源器件的栅极至漏极电容为Cgd1，Cgd1≠Cgd2。

公开(公告)号：US20120169956A1

公开(公告)日：2012-07-05

申请号：US13118446

申请日：2011-05-29

Applicant: Chun-Chi Lai ,  Ching-Wei Chen ,  Tsan-Chun Wang ,  Kuo-Hsing Cheng ,  Yu-Cheng Chen

Inventor： Chun-Chi Lai ,  Ching-Wei Chen ,  Tsan-Chun Wang ,  Kuo-Hsing Cheng ,  Yu-Cheng Chen

IPC: G02F1/136

CPC classification number: G02F1/136213 ,  G02F1/136286 ,  G02F2001/134345 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2310/0205 ,  G09G2310/0213 ,  G09G2320/0214 ,  H01L27/1251

Abstract: An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels.

Abstract translation: LCD面板通过数据线将显示数据以锯齿形图案发送到子像素。 子像素的馈通电压的变化可以通过调整子像素中的TFT的沟道宽度和沟道长度的比率达到一些预定的比率来修改，或者通过调整对耦合的补偿电容 子像素的TFT的电容。

公开(公告)号：US20120115288A1

公开(公告)日：2012-05-10

申请号：US13349586

申请日：2012-01-13

Applicant: Ming-Wei Sun ,  Chen-Yueh Li ,  Yu-Cheng Chen ,  Chia-Tien Peng

Inventor： Ming-Wei Sun ,  Chen-Yueh Li ,  Yu-Cheng Chen ,  Chia-Tien Peng

IPC: H01L21/336

CPC classification number: H01L27/14692 ,  H01L27/1214 ,  H01L27/1288 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14645

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract translation: 提供一种用于制造有源器件阵列衬底的方法。 第一图案化半导体层，栅极绝缘体，第一图案化导电层和第一介电层依次形成在衬底上。 暴露第一图案化半导体层的第一接触孔形成在第一介电层和栅极绝缘体中。 第一图案化导电层和设置在其上的第二图案化半导体层同时形成在第一介电层上。 第二导电层包括接触导体和底部电极。 第二图案化半导体层包括有源层。 具有第二接触孔的第二电介质层形成在第一电介质层上，其中一部分第二接触孔露出有源层。 通过第二接触孔的一部分电连接到有源层的第三图案化导电层形成在第二介电层上。

公开(公告)号：US08072566B2

公开(公告)日：2011-12-06

申请号：US12879006

申请日：2010-09-10

Applicant: Yu-Cheng Chen ,  Tun-Chun Yang

Inventor： Yu-Cheng Chen ,  Tun-Chun Yang

IPC: G02F1/1335

CPC classification number: G02F1/133555 ,  H01L27/124 ,  H01L27/1248

Abstract: A method of forming a transflective LCD panel is provided. The transflective LCD includes a substrate, a first polycrystalline silicon pattern disposed in a reflection region, a second polycrystalline silicon pattern disposed in a peripheral region, an insulating layer disposed on the first and second polycrystalline silicon pattern and the substrate, a gate electrode disposed in the reflection region, a common electrode disposed in the peripheral region, a first inter-layer dielectric disposed on the insulating layer, the gate electrode and the common electrode, a reflection electrode disposed on the first inter-layer dielectric, a second inter-layer dielectric disposed on the first inter-layer dielectric and the reflection electrode, and a transmission electrode disposed on the second inter-layer dielectric and electrically connected to the reflection electrode through an opening of the second inter-layer dielectric. The second polycrystalline silicon pattern, the common electrode, and the insulating layer disposed therebetween form a storage capacitor.

Abstract translation: 提供了一种形成透反液晶显示面板的方法。 半透射型LCD包括基板，设置在反射区域中的第一多晶硅图案，设置在周边区域中的第二多晶硅图案，设置在第一和第二多晶硅图案和基板上的绝缘层，设置在 反射区域，设置在周边区域中的公共电极，设置在绝缘层上的第一层间电介质，栅电极和公共电极，设置在第一层间电介质上的反射电极，第二层间电介质 布置在第一层间电介质和反射电极上的电介质，以及设置在第二层间电介质上并通过第二层间电介质的开口与反射电极电连接的透射电极。 第二多晶硅图案，公共电极和设置在其间的绝缘层形成存储电容器。

公开(公告)号：US20110292331A1

公开(公告)日：2011-12-01

申请号：US12909831

申请日：2010-10-22

Applicant: Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen ,  Tsan-Chun Wang

Inventor： Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen ,  Tsan-Chun Wang

IPC: G02F1/1333

CPC classification number: G02F1/13624 ,  G02F2001/13606

Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.

Abstract translation: 像素结构包括第一和第二扫描线，数据线，覆盖第一和第二扫描线的第一绝缘层和数据线的一部分并具有凹部，覆盖第一绝缘层的第二绝缘层， 覆盖数据线和凹部的电容器电极线，电容器电极线上的第三绝缘层，与第二扫描线和数据线电连接的第一有源器件，与第一有源器件电连接的第二有源器件，以及 第一扫描线以及分别电连接到第一和第二有源器件的第一和第二像素电极。 数据线和第一和第二扫描线的部分在同一层中。 凹槽位于数据线部分的两侧。

公开(公告)号：US20110156038A1

公开(公告)日：2011-06-30

申请号：US12770737

申请日：2010-04-30

Applicant: Ching-Jung Yang ,  Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen

Inventor： Ching-Jung Yang ,  Ke-Chih Chang ,  Kuo-Yu Huang ,  Yu-Cheng Chen

IPC: H01L27/12 ,  H01L29/786

CPC classification number: G02F1/136213 ,  G02F1/133371 ,  G02F1/133504 ,  G02F1/133555 ,  G02F1/136227 ,  H01L27/1255

Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.

Abstract translation: 提供了包括衬底，扫描线，数据线，有源器件，第一介电层，公共线，第二电介质层，图案化导电层，第三电介质层和像素电极的有源器件阵列衬底。 有源器件的至少一部分电连接到扫描线和数据线。 第一介电层覆盖扫描线，数据线和有源器件。 公共线设置在第一电介质层上。 第二介电层覆盖公共线和第一介电层。 图案化导电层设置在第二介电层上。 第三电介质层覆盖图案化的导电层和第二介电层。 像素电极设置在第三电介质层上并电连接到图案化导电层和有源器件。

公开(公告)号：US07851801B2

公开(公告)日：2010-12-14

申请号：US11963853

申请日：2007-12-24

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L29/76

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。