公开(公告)号：US4964142A

公开(公告)日：1990-10-16

申请号：US72955

申请日：1987-07-15

Applicant: Kadiresan Annamalai

Inventor： Kadiresan Annamalai

IPC: H04L7/00 ,  H04J3/06

CPC classification number: H04J3/0632

Abstract: Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

公开(公告)号：US4617478A

公开(公告)日：1986-10-14

申请号：US530176

申请日：1983-09-07

Applicant: Hemmige D. Varadarajan

Inventor： Hemmige D. Varadarajan

IPC: H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086 ,  H03K19/082 ,  H03K19/092

CPC classification number: H03K19/086 ,  H03K19/013

Abstract: In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.

Abstract translation: 根据本发明，在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关的参考部分通过引入一个慢速装置作为参考元件来修改，以增强输入元件的导通和关断速度 。 特别地，传统的ECL逆变器栅极或常规CML反相器栅极的参考晶体管被替换为慢晶体管或慢二极管，以便绕过发射极动态电阻。 因此，参考元件QR的发射极时间常数增加，使得当输入元件的基极瞬时变化时，公共电流源节点（节点3）上的电压基本上不变化。 因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。

公开(公告)号：US20250165284A1

公开(公告)日：2025-05-22

申请号：US18518204

申请日：2023-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Travis Boraten ,  Heather Lynn Hanson ,  Yasuko Eckert ,  Onur Kayiran

IPC: G06F9/48

Abstract: A method for collapsing operations into super operations in a computing system includes dispatching a super operation corresponding to a collapsible sequence of operations to a scheduler, performing a lookup in a super operation table for the collapsible sequence of operations in response to the super operation being picked from the scheduler, and multi-pumping the collapsible sequence of operations to a pipe operationally coupled to the scheduler. For example, the multi-pumped collapsible sequence of operations may then be sequentially executed by an execution unit. The collapsible sequence of operations may be identified as collapsible according to a set of rules.

公开(公告)号：US20250156329A1

公开(公告)日：2025-05-15

申请号：US18388940

申请日：2023-11-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan Kalyanasundharam ,  Christopher J. Brennan ,  Joseph L. Greathouse ,  Mark Fowler

IPC: G06F12/0862 ,  G06F13/28

Abstract: A processing system includes one or more DMA engines that load data from memory or another cache location without storing the data after loading it. As the data propagates past caches located between the memory or other cache location that stores the requested data (“intermediate caches”), the data is selectively copied to the intermediate caches based on a cache replacement policy. Rather than the DMA engine manually storing the data into the intermediate caches, the cache replacement policies of the intermediate caches determine whether the data is copied into each respective cache and a replacement priority of the data. By bypassing storing the data, the DMA engine effectuates prefetching to the intermediate caches without expending unnecessary bandwidth or searching for a memory location to store the data, thus reducing latency and saving energy.

公开(公告)号：US12300311B1

公开(公告)日：2025-05-13

申请号：US17971763

申请日：2022-10-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Sahilpreet Singh ,  Russell Schreiber

IPC: G11C11/418

Abstract: A multipurpose wordline underdrive circuit includes a wordline driver and a pulldown network. The pulldown network includes a first current-carrying terminal electrically coupled to the wordline driver and a second current-carrying terminal electrically coupled to a control signal. The pulldown network also includes a current-regulation terminal electrically coupled to an additional control signal. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US12299297B2

公开(公告)日：2025-05-13

申请号：US18216109

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Jean J. Chittilappilly ,  Tahsin Askar ,  James R. Magro

IPC: G06F3/06

Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

公开(公告)号：US12298829B2

公开(公告)日：2025-05-13

申请号：US18213596

申请日：2023-06-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/00 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/26 ,  G06F1/3203

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US20250149525A1

公开(公告)日：2025-05-08

申请号：US18615918

申请日：2024-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Alan D. SMITH ,  Raja SWAMINATHAN

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H10B80/00

Abstract: Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.

公开(公告)号：US20250148645A1

公开(公告)日：2025-05-08

申请号：US18386655

申请日：2023-11-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Navin Patel ,  Shashank Ranjan

IPC: G06T9/00

Abstract: A processing system preconditions block-compressed texture blocks by separately streaming color components and index components for lossless compression. The processing system preconditions the color components for linear compression, such that color component data for adjacent compressed blocks in a row are further compressed using lossless compression. Lossless compression is performed for color components spanning multiple rows to leverage patterns in color components that extend vertically across a frame. The processing system further divides input color component and index component data into pages of memory (e.g., 64 kB pages), such that each page can be independently losslessly compressed and decompressed. The processing system applies delta encoding to color component data so that a single instance of color data and differences from the stored color data are stored for each page.

公开(公告)号：US12293092B2

公开(公告)日：2025-05-06

申请号：US18083306

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lu Lu ,  Anthony Asaro ,  Yinan Jiang

IPC: G06F3/06

Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.