公开(公告)号：US20250079333A1

公开(公告)日：2025-03-06

申请号：US18390626

申请日：2023-12-20

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao LIN ,  Chiao-Cheng CHANG ,  Chien-Wei CHANG

IPC: H01L23/00 ,  H01L23/498

Abstract: An anti-warpage reinforced carrier includes a substrate, a plurality of rigid insulating plates, a plurality of metal posts, a resin layer, a first circuit layer, and a second circuit layer. The rigid insulating plates are arranged on the positioning areas on the substrate. The metal posts are in the second through holes penetrating through the rigid insulating plate. The resin layer covers the rigid insulating plates and the upper surface of the substrate, and includes a plurality of openings. The first circuit layer is on the resin layer and in the openings, and is connected to the metal posts. The second circuit layer is on a lower surface of the substrate and in the first through holes penetrating through the substrate, and is connected to the metal posts. By embedding rigid insulating plates therein, the anti-warpage reinforced carrier provides thermal stability, and is suitable for applications in advanced chip packaging.

公开(公告)号：US10779418B2

公开(公告)日：2020-09-15

申请号：US16555261

申请日：2019-08-29

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

Abstract: A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

公开(公告)号：US10548214B2

公开(公告)日：2020-01-28

申请号：US15826694

申请日：2017-11-30

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chin-Kuan Liu ,  Chao-Lung Wang ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Chin-Hsi Chang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/06

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.

公开(公告)号：US10455694B2

公开(公告)日：2019-10-22

申请号：US16408431

申请日：2019-05-09

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chin-Kuan Liu ,  Chao-Lung Wang ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Chin-Hsi Chang

IPC: H01K3/10 ,  H05K1/02 ,  H05K3/46 ,  H05K1/09 ,  H05K3/06 ,  H01L21/48

Abstract: A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.

公开(公告)号：US10366822B2

公开(公告)日：2019-07-30

申请号：US16280435

申请日：2019-02-20

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01F5/00 ,  H01F7/06 ,  H01F27/28 ,  H05K3/00 ,  H05K1/00 ,  H05K1/16 ,  H01F41/04 ,  H05K3/46

Abstract: A method of manufacturing a winged coil structure is provided. The method includes preparing an upper flexible plate having a middle region and two side regions bordering the middle region; preparing a dielectric layer with a lateral size of the dielectric layer being the same as a lateral size of the middle region of the upper flexible plate; preparing a lower flexible plate having a middle region and two side regions bordering the middle region; preparing a bottom flexible plate attached to the lower surface of the lower flexible plate to form a stack body; and performing a process of thermal pressing to sequentially from bottom to top stack and combine the stack body, the dielectric layer, and the upper flexible plate as a multiple layered stack structure via a press mold.

公开(公告)号：US10170403B2

公开(公告)日：2019-01-01

申请号：US14572904

申请日：2014-12-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nung Lin

IPC: H01L23/498

Abstract: An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the prior art replaced by an anisotropic conductive film or materials with similar structure. The anisotropic conductive film has conductive particles therein to replace the conductive openings on the insulating layer in the prior art. When compressing the substrate onto the carrier board, the bottom surface of the second electrode pads are compressing the corresponding conductive particles on the second electrical contact pads, causing which to burst, therefore forming high-density compressed areas that conduct the second electrode pads and the second electrical contact pads; the conductive particles outside the high-density compressed area are not burst, forming an insulating film between the substrate and the carrier board; in other words, the anisotropic conductive film provides conduction in a Z direction. The structure can avoid the inaccuracies of distance and size of the conductive openings and the inaccuracy of the contact between the second electrode pads and the second electrical contact pads.

公开(公告)号：US10104817B1

公开(公告)日：2018-10-16

申请号：US15859982

申请日：2018-01-02

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. The EMI shielding device is adopted to be mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US09967975B2

公开(公告)日：2018-05-08

申请号：US15143354

申请日：2016-04-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K1/09 ,  H05K1/0298 ,  H05K1/144 ,  H05K3/4614 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09472

Abstract: A multi-layer circuit board includes a first circuit board, multiple conducting blocks, a second circuit board, and multiple conducting recesses. The first circuit board has a first conductor layer formed thereon. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the surface of the second circuit board. Each conducting recess has a conducting layer electrically connected to the second conductor layer. When the conducting blocks are mounted in the conducting recesses, the first conductor layer and the second conductor layer are electrically connected through the conducting blocks and the conducting recesses. As can be separated from the first circuit board for test of the two conductor layers, the yield of the second circuit board is enhanced.

公开(公告)号：US09370110B2

公开(公告)日：2016-06-14

申请号：US14225682

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/10 ,  H05K3/28 ,  H05K3/34

CPC classification number: H05K3/4611 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/06 ,  H05K2203/0723 ,  H05K2203/143

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract translation: 制造多层基板结构的方法包括预处理，压制和后处理的步骤。 设置有电路图案层的承载板被压靠在塑料片上。 通过钻孔和填充塑料片的下表面形成夹层连接垫。 将载板，塑料片，另一塑料片和具有电路图案层的另一载体板压在一起，然后钻孔/填充以形成多层堆叠结构，使得两个电路图案层间接地并电连接到中间层 连接垫。 因此，可以通过使用比对准公差宽的层间连接焊盘来克服由于对准公差引起的问题，并且堆叠各个具有更细的线和更小间距的电路层。

公开(公告)号：US20150282333A1

公开(公告)日：2015-10-01

申请号：US14225682

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/46 ,  H05K3/34 ,  H05K3/28 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K3/4611 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/06 ,  H05K2203/0723 ,  H05K2203/143

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract translation: 制造多层基板结构的方法包括预处理，压制和后处理的步骤。 设置有电路图案层的承载板被压靠在塑料片上。 通过钻孔和填充塑料片的下表面形成夹层连接垫。 将载板，塑料片，另一塑料片和具有电路图案层的另一载体板压在一起，然后钻孔/填充以形成多层堆叠结构，使得两个电路图案层间接地并电连接到中间层 连接垫。 因此，可以通过使用比对准公差宽的层间连接焊盘来克服由于对准公差引起的问题，并且堆叠各个具有更细的线和更小间距的电路层。