公开(公告)号：US09379696B2

公开(公告)日：2016-06-28

申请号：US14294176

申请日：2014-06-03

Applicant: Maxchip Electronics Corp.

Inventor： Ming-Chi Kuo ,  Tsung-Chih Tsai ,  Jen-Yao Hsu

IPC: H03K17/16 ,  H03K17/14 ,  H03K17/687 ,  H03K17/06

CPC classification number: H03K17/145 ,  H03K17/063 ,  H03K17/162 ,  H03K17/6871 ,  H03K2017/6875 ,  H03K2217/0054 ,  H03K2217/0081

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

Abstract translation: 提供了一种高压自举门驱动装置。 栅极驱动装置包括高端晶体管，低端晶体管，缓冲器，升压电容器和高电压耗尽晶体管。 高端晶体管接收第一电源电压。 缓冲器根据偏置电压向高端晶体管提供高端驱动信号。 升压电容器串联耦合在基极电压和偏置电压之间。 耗尽晶体管的第一端耦合到第二电源电压，耗尽型晶体管的第二端耦合到偏置电压，耗尽晶体管的控制端接收参考接地电压。

公开(公告)号：US20150333140A1

公开(公告)日：2015-11-19

申请号：US14277809

申请日：2014-05-15

Applicant: Maxchip Electronics Corp.

Inventor： Kosuke Yoshida

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/764 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor structure is provided. An N-type epitaxial layer is disposed on an N-type substrate. The N-type epitaxial layer has at least one trench therein, wherein the trench has a straight sidewall. A first insulating layer is disposed on at least a portion of a surface of the trench. A silicon-containing layer is disposed in a lower portion of the trench and has at least one air gap therein. A first conductive layer is disposed in an upper portion of the trench. Two P-type well regions are disposed in the N-type epitaxial layer beside the trench. Two N-type source regions are respectively disposed in the P-type well regions beside the trench.

Abstract translation: 提供半导体结构。 在N型衬底上设置N型外延层。 N型外延层在其中具有至少一个沟槽，其中沟槽具有直的侧壁。 第一绝缘层设置在沟槽的表面的至少一部分上。 含硅层设置在沟槽的下部，并在其中具有至少一个气隙。 第一导电层设置在沟槽的上部。 在沟槽旁边的N型外延层中设置两个P型阱区。 两个N型源极区域分别设置在沟槽旁边的P型阱区域中。

公开(公告)号：US20140008653A1

公开(公告)日：2014-01-09

申请号：US14020908

申请日：2013-09-09

Applicant: Maxchip Electronics Corp.

Inventor： Jin-Wei Chang ,  Hung-Lung Wang ,  Jung-Kai Hung

IPC: H01L27/146

CPC classification number: H01L27/14649 ,  G01J1/02 ,  G01J1/029 ,  G01J1/08 ,  G01J1/4204 ,  G01J1/4228 ,  G01J3/36 ,  G01J5/0846 ,  H01L27/1443 ,  H01L27/14621 ,  H01L27/14652

Abstract: Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region.

Abstract translation: 提供了与包括基板，IR感测结构，电介质层和多波段光感测结构的红外线（IR）感测功能相结合的多波段光束传感器。 衬底包括第一区域和第二区域。 IR感测结构位于用于感测IR的基板中。 电介质层位于IR感测结构上。 多波段光束感测结构包括第一波段光传感器，第二波段光传感器和第三波段光传感器。 第二波段光传感器和第一波段光传感器从底部向上叠置并设置在基板的第一区域上的IR感测结构上。 第三波段光传感器位于第二区域的介质层中。

公开(公告)号：US20110108728A1

公开(公告)日：2011-05-12

申请号：US12696026

申请日：2010-01-28

Applicant: Jin-Wei Chang ,  Jen-Yao Hsu ,  Hong-Xian Wang ,  Yu-Hsien Chen

Inventor： Jin-Wei Chang ,  Jen-Yao Hsu ,  Hong-Xian Wang ,  Yu-Hsien Chen

IPC: G01J5/20 ,  H01L31/0376

CPC classification number: G01J1/4228 ,  G01J1/02 ,  G01J1/029 ,  G01J1/08 ,  G01J1/4204 ,  G01J5/0846 ,  H01L27/1443

Abstract: An ambit light sensor with a function of IR sensing and a method of fabricating the same are provided. The ambit light sensor includes a substrate, an ambit light sensing structure, an infrared ray (IR) sensing structure, and a dielectric layer. The ambit light sensing structure is located over the substrate for sensing and filtering visible light. The IR sensing structure is located in the substrate under the ambit light sensing structure for sensing IR. The dielectric layer is located between the ambit light sensing structure and the IR sensing structure.

Abstract translation: 提供了一种具有IR感测功能的光束传感器及其制造方法。 该载流子传感器包括基板，横截面光感测结构，红外线（IR）感测结构和电介质层。 该位移光感测结构位于衬底上，用于感测和过滤可见光。 IR感测结构位于用于感测IR的光束感测结构下的衬底中。 电介质层位于光束感测结构和IR感测结构之间。

公开(公告)号：US09142583B2

公开(公告)日：2015-09-22

申请号：US14089769

申请日：2013-11-26

Applicant: Maxchip Electronics Corp.

Inventor： Jin-Wei Chang ,  Hung-Lung Wang ,  Jung-Kai Hung ,  Wei-Chi Su

IPC: H01L27/146 ,  H01L27/144

CPC classification number: H01L27/1463 ,  H01L27/1443 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14647 ,  H01L27/14652

Abstract: Provided is a light sensor including a substrate, a dielectric layer, a plurality of pixels, a plurality of spacers, and a plurality of metal interconnects. The dielectric layer is located on the substrate. The pixels are located in the dielectric layer. The spacers are located on the sidewall of openings between adjacent pixels. The metal interconnects are located in the openings and cover the spacers so as to be electrically connected to the corresponding pixels.

Abstract translation: 提供一种光传感器，其包括基板，电介质层，多个像素，多个间隔物和多个金属互连。 电介质层位于衬底上。 像素位于电介质层中。 间隔物位于相邻像素之间的开口的侧壁上。 金属互连件位于开口中并且覆盖间隔件以便电连接到相应的像素。

公开(公告)号：US20150091123A1

公开(公告)日：2015-04-02

申请号：US14089769

申请日：2013-11-26

Applicant: Maxchip Electronics Corp.

Inventor： Jin-Wei Chang ,  Hung-Lung Wang ,  Jung-Kai Hung ,  Wei-Chi Su

IPC: H01L27/144 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1443 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14647 ,  H01L27/14652

Abstract: Provided is a light sensor including a substrate, a dielectric layer, a plurality of pixels, a plurality of spacers, and a plurality of metal interconnects. The dielectric layer is located on the substrate. The pixels are located in the dielectric layer. The spacers are located on the sidewall of openings between adjacent pixels. The metal interconnects are located in the openings and cover the spacers so as to be electrically connected to the corresponding pixels.

Abstract translation: 提供一种光传感器，其包括基板，电介质层，多个像素，多个间隔物和多个金属互连。 电介质层位于衬底上。 像素位于电介质层中。 间隔物位于相邻像素之间的开口的侧壁上。 金属互连件位于开口中并且覆盖间隔件以便电连接到相应的像素。

公开(公告)号：US20130043522A1

公开(公告)日：2013-02-21

申请号：US13244640

申请日：2011-09-25

Applicant: Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

Inventor： Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

IPC: H01L27/07 ,  H01L21/8239

CPC classification number: H01L29/66825 ,  H01L27/11517 ,  H01L27/11526 ,  H01L28/20

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 在单元区域中的基板上形成包括栅极氧化物层，浮置栅极和第一间隔物的层叠结构，并且在周边区域的基板上形成电阻体。 在堆叠结构旁边的衬底中形成至少两个掺杂区域。 介电材料层和导电材料层依次形成在基板上。 在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。 除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层，以在叠层结构上形成栅极间电介质层和控制栅极，同时在电阻器上形成自对准硅化物阻挡层。

公开(公告)号：US20120211096A1

公开(公告)日：2012-08-23

申请号：US13114018

申请日：2011-05-23

Applicant: Huan-Che Huang ,  Kuan-Ting Chen ,  Chih-Chang Chen

Inventor： Huan-Che Huang ,  Kuan-Ting Chen ,  Chih-Chang Chen

IPC: F16K15/02

CPC classification number: F16K51/02 ,  F16K15/06 ,  F16K15/18 ,  F16K31/122 ,  Y10T137/7904

Abstract: A check valve includes a case body, a piston device, and a blocking plate. The case body includes a first case part and a second case part. The first case part has a first opening. The second case part has a second opening and a third opening. The second opening faces the first opening, and the third opening is located at one side of the second opening. The first case part and the second case part are combined to form the case body, and the case body has a fluid passage therein. The piston device is aligned to the second opening and mounted on the second case part. The blocking plate is disposed on the piston device. When the piston device operates, the piston device pushes the blocking plate to seal the first opening.

Abstract translation: 止回阀包括壳体，活塞装置和阻挡板。 壳体包括第一壳体部分和第二壳体部分。 第一个病例部分有第一个开口。 第二壳体部分具有第二开口和第三开口。 第二开口面向第一开口，第三开口位于第二开口的一侧。 第一壳体部分和第二壳体部分组合以形成壳体，并且壳体在其中具有流体通道。 活塞装置对准第二开口并安装在第二壳体部分上。 阻挡板设置在活塞装置上。 当活塞装置工作时，活塞装置推动阻挡板以密封第一开口。

公开(公告)号：US08134708B2

公开(公告)日：2012-03-13

申请号：US12337606

申请日：2008-12-17

Applicant: Chien-Min Wu ,  Chien-Chih Chen

Inventor： Chien-Min Wu ,  Chien-Chih Chen

IPC: G01B11/00

CPC classification number: G01B11/26 ,  G03B27/42 ,  G03F7/706

Abstract: A method of measuring a numerical aperture of an exposure machine is described. A control wafer having vernier marks thereon and an aberration mask having pinholes therein are provided, wherein each pinhole corresponds to a vernier mark in position. A lithography process using the exposure machine and the aberration mask is performed to the control wafer, so as to form over each vernier mark a photoresist pattern having the same shape of the illumination pattern of the light source of the exposure machine. The numerical aperture of the exposure machine is then derived from a graduation of the vernier mark corresponding to an outer edge of the photoresist pattern.

Abstract translation: 描述了一种测量曝光机的数值孔径的方法。 提供其上具有游标标记的对照晶片和其中具有针孔的像差掩模，其中每个针孔对应于位置上的游标标记。 对控制晶片执行使用曝光机和像差掩模的光刻处理，以在每个游标标记上形成具有与曝光机的光源的照明图案相同形状的光致抗蚀剂图案。 然后，曝光机的数值孔径从对应于光致抗蚀剂图案的外边缘的游标标记的刻度得到。

公开(公告)号：US20190252369A1

公开(公告)日：2019-08-15

申请号：US15975791

申请日：2018-05-10

Applicant: Maxchip Electronics Corp.

Inventor： Ruei-Siang Syu ,  Wen-Chu Lo ,  Chih-Feng Lin

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/067 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/7436

Abstract: An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.