公开(公告)号：US07869549B2

公开(公告)日：2011-01-11

申请号：US11115437

申请日：2005-04-27

Applicant: Fang Yang ,  Shunbai Tang

Inventor： Fang Yang ,  Shunbai Tang

IPC: H04L27/08

CPC classification number: H03G3/3036 ,  H03G3/30

Abstract: A method of gain control by amplifying an input signal with a variable gain amplifier to generate an output signal where the gain of the variable gain amplifier is selected based upon a control signal presented at a control input of the variable gain amplifier. When the output signal is larger than the upper boundary, incrementally changing the magnitude of the control signal so as to reduce the gain of the variable gain amplifier in a step-wise linear fashion. When the output signal is smaller than the lower boundary, incrementally changing the magnitude of the control signal so as to increase the gain of the variable gain amplifier in a step-wise linear fashion.

Abstract translation: 一种通过用可变增益放大器放大输入信号以产生输出信号的增益控制的方法，其中可变增益放大器的增益基于在可变增益放大器的控制输入处呈现的控制信号而被选择。 当输出信号大于上边界时，逐步改变控制信号的幅度，以逐步线性的方式减小可变增益放大器的增益。 当输出信号小于下边界时，逐步改变控制信号的幅度，以逐步线性的方式增加可变增益放大器的增益。

公开(公告)号：US07737769B2

公开(公告)日：2010-06-15

申请号：US12049127

申请日：2008-03-14

Applicant: Yun Fei Deng ,  Shun Bai Tang

Inventor： Yun Fei Deng ,  Shun Bai Tang

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core.

Abstract translation: 电路包括连接在调节电压和接地参考之间的无OPAMP的带隙电压产生核心电路，以产生输出带隙电压。 预调节器电路从未调节的电源电压产生调节电压。 预调节器电路包括可操作以稳定调节电压的负反馈回路和可操作以为调节电压源电流的电流源，该电流源镜像无OPAMP的带隙电压产生核心电路的PTAT电流。 核心电路还包括负反馈回路和正反馈回路，负和正反馈回路用于均衡内核内的两个内部电压。

公开(公告)号：US07622874B2

公开(公告)日：2009-11-24

申请号：US11693989

申请日：2007-03-30

Applicant: Chunxing Deng ,  Wenli Luo

Inventor： Chunxing Deng ,  Wenli Luo

IPC: H02H7/09

CPC classification number: H02H7/0838

Abstract: A motor driver includes an H-bridge having a first differential input, a second differential input, and a differential output; a sensing circuit coupled to the differential output of the H-bridge; a comparison and logic circuit coupled to the sensing circuit; a pair of pre-driver circuits coupled to the comparison and logic circuit for driving at least one of the differential inputs of the H-bridge; and a pair of level shifters coupled between the comparison and logic circuit and the sensing circuit. The pair of level shifters is used to assure that the VGS of a pair of serially coupled transistors in the sensing circuit do not change with temperature, motor current, or voltage, and each includes a transistor receiving a reference current. The pair of level shifters each further includes a serially coupled diode and zener diode for preventing current from flowing from the differential output of the H-bridge to the level-shifting transistor.

Abstract translation: 电机驱动器包括具有第一差分输入，第二差分输入和差分输出的H桥; 耦合到H桥的差分输出的感测电路; 耦合到感测电路的比较和逻辑电路; 耦合到比较和逻辑电路的一对预驱动器电路，用于驱动H桥的差分输入中的至少一个; 以及耦合在比较逻辑电路和感测电路之间的一对电平移位器。 该对电平转换器用于确保感测电路中的一对串联耦合晶体管的VGS不随着温度，电动机电流或电压而改变，并且每个包括接收参考电流的晶体管。 该对电平移位器还包括串联耦合的二极管和齐纳二极管，用于防止电流从H桥的差分输出流到电平移位晶体管。

公开(公告)号：US20090174391A1

公开(公告)日：2009-07-09

申请号：US11970435

申请日：2008-01-07

Applicant: Haibo Zhang ,  Ligang Jia

Inventor： Haibo Zhang ,  Ligang Jia

IPC: G01R19/15

CPC classification number: G01R19/175 ,  H02M2001/0009

Abstract: A zero current detector for a DC-DC converter includes a first transistor having a drain, a gate, and a source for sensing the voltage of a first terminal of a power transistor; a second transistor having a drain, a gate, and a source for sensing the voltage of a second terminal of a power transistor; and a third transistor having a coupled gate and drain for receiving a reference current that is coupled to the gates of the first and second transistors and a source coupled to the source of the first transistor, wherein an output signal is provided by the drains of the first and second transistors. A load is coupled to the drains of the first and second transistors. The zero current detector also includes a fourth transistor having a current path coupled between the source of the second transistor and the second terminal of the power transistor and a gate for receiving a control signal.

Abstract translation: 用于DC-DC转换器的零电流检测器包括具有漏极，栅极和源极的第一晶体管，用于感测功率晶体管的第一端子的电压; 具有用于感测功率晶体管的第二端子的电压的漏极，栅极和源极的第二晶体管; 以及第三晶体管，其具有用于接收耦合到所述第一和第二晶体管的栅极的参考电流的耦合栅极和漏极以及耦合到所述第一晶体管的源极的源极，其中输出信号由所述第一和第二晶体管的漏极提供， 第一和第二晶体管。 负载耦合到第一和第二晶体管的漏极。 零电流检测器还包括具有耦合在第二晶体管的源极和功率晶体管的第二端子之间的电流通路的第四晶体管和用于接收控制信号的栅极。

公开(公告)号：US20080279090A1

公开(公告)日：2008-11-13

申请号：US12079927

申请日：2008-03-28

Applicant: Yan Liu ,  Huazhong Yang

Inventor： Yan Liu ,  Huazhong Yang

IPC: H04J11/00

CPC classification number: H04L27/265 ,  H04H2201/12 ,  H04L27/0008

Abstract: A Digital Radio Mondiale (DRM) receiver and demodulation method includes an analog and digital separation filter for filtering and separating a DRM-encoded signal and a non DRM-encoded signal from a composite RF signal received at the receiver. The DRM receiver includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. The structure and operation of the receiver in this manner simplifies the design and reduces the required filter order of the analog and digital separation filter.

Abstract translation: 数字无线电广播（DRM）接收机和解调方法包括模拟和数字分离滤波器，用于从在接收机处接收的复合RF信号过滤和分离DRM编码信号和非DRM编码信号。 DRM接收机包括可编程下行采样器和可编程N点快速傅里叶变换（FFT），以在接收的DRM编码RF信号中恢复和解调OFDM符号。 所接收的信号以可操作地整数下采样的速率进行数字采样，以在OFDM符号的有用部分中实现N个采样，以输入到N点FFT，其中N等于2的幂。 FFT的下采样率和大小（N点）取决于DRM编码和传输参数，特别是鲁棒性模式和频谱占用。 以这种方式，接收机的结构和操作简化了设计，并减少了模拟和数字分离滤波器所需的滤波器顺序。

公开(公告)号：US20080278870A1

公开(公告)日：2008-11-13

申请号：US11693989

申请日：2007-03-30

Applicant: Chunxing Deng ,  Wenli Luo

Inventor： Chunxing Deng ,  Wenli Luo

IPC: H02H7/08

CPC classification number: H02H7/0838

Abstract: A motor driver having over current detection circuitry includes an H-bridge having a first differential input, a second differential input, and a differential output; a sensing circuit coupled to the differential output of the H-bridge; a comparison and logic circuit coupled to the sensing circuit; a pair of pre-driver circuits coupled to the comparison and logic circuit for driving at least one of the differential inputs of the H-bridge; and a pair of level shifters coupled between the comparison and logic circuit and the sensing circuit. The H-bridge includes a first side having a first transistor coupled to a second transistor, and a second side having a third transistor coupled to a fourth transistor. The first and third transistors are power PDMOS transistors, and the second and fourth transistors are power NDMOS transistors. The pair of level shifters are used to assure that the VGS of a pair of serially coupled transistors in the sensing circuit do not change with temperature, motor current, or voltage, and each include a transistor receiving a reference current. The pair of level shifters each further includes a serially coupled diode and zener diode for preventing current from flowing from the differential output of the H-bridge to the level-shifting transistor.

Abstract translation: 具有过电流检测电路的电机驱动器包括具有第一差分输入，第二差分输入和差分输出的H桥; 耦合到H桥的差分输出的感测电路; 耦合到感测电路的比较和逻辑电路; 耦合到比较和逻辑电路的一对预驱动器电路，用于驱动H桥的差分输入中的至少一个; 以及耦合在比较逻辑电路和感测电路之间的一对电平移位器。 H桥包括具有耦合到第二晶体管的第一晶体管的第一侧和具有耦合到第四晶体管的第三晶体管的第二侧。 第一和第三晶体管是功率PDMOS晶体管，第二和第四晶体管是功率NDMOS晶体管。 该对电平转换器用于确保感测电路中的一对串联耦合的晶体管的V GS不随着温度，电动机电流或电压而改变，并且每个包括接收 参考电流。 该对电平移位器还包括串联耦合的二极管和齐纳二极管，用于防止电流从H桥的差分输出流到电平移位晶体管。

公开(公告)号：US07191301B2

公开(公告)日：2007-03-13

申请号：US10033204

申请日：2001-12-26

Applicant: Lijun Tian

Inventor： Lijun Tian

IPC: G06F12/00 ,  H04B7/26

CPC classification number: H04B14/04

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address (es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract translation: 微控制器连接在基于硬件的自适应差分脉码调制（ADPCM）解码器和存储微控制器编程指令和ADPCM编码的源文件数据的只读存储器（ROM）之间。 微控制器架构实现由两相时钟信号驱动的时间复用ROM寻址。 在指令阶段，程序计数器提供用于检索微控制器编程指令的ROM地址。 在解码器阶段，地址计数器提供用于检索ADPCM编码的源文件数据的部分的ROM地址。 在时钟信号的解码器相位中从ROM提取的ADPCM编码的源文件数据被传送到解码器，以在时钟信号的后续指令阶段进行处理。 应用于ROM的程序计数器和地址计数器提供的地址之间的选择由两相时钟信号驱动的多路复用器进行。

公开(公告)号：US20230135498A1

公开(公告)日：2023-05-04

申请号：US18050413

申请日：2022-10-27

Applicant: STMICROELECTRONICS S.r.l. ,  SHENZHEN STS MICROELECTRONICS CO., LTD.

Inventor： Yi Ming LIANG ,  Roberto TIZIANI ,  Qian LIU ,  Feng DING

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L23/373

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

公开(公告)号：US08295372B2

公开(公告)日：2012-10-23

申请号：US12079953

申请日：2008-03-28

Applicant: Yan Liu ,  Huazhong Yang

Inventor： Yan Liu ,  Huazhong Yang

IPC: H04K1/10

CPC classification number: H04L27/265 ,  H04B1/0003

Abstract: A Digitial Radio Mondiale (DRM) receiver and demodulation method includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. This reduces the processing/computational requirements and the design complexity of the DRM receiver.

Abstract translation: 数字无线电广播（DRM）接收机和解调方法包括可编程下行采样器和可编程N点快速傅里叶变换（FFT），以便在接收的DRM编码RF信号中恢复和解调OFDM符号。 所接收的信号以可操作地整数下采样的速率进行数字采样，以在OFDM符号的有用部分中实现N个采样，以输入到N点FFT，其中N等于2的幂。 FFT的下采样率和大小（N点）取决于DRM编码和传输参数，特别是鲁棒性模式和频谱占用。 这降低了DRM接收机的处理/计算要求和设计复杂度。

公开(公告)号：US08270503B2

公开(公告)日：2012-09-18

申请号：US12079951

申请日：2008-03-28

Applicant: Yan Liu

Inventor： Yan Liu

IPC: H04L27/28

CPC classification number: H04L27/2657 ,  H04L27/2675 ,  H04L27/2684

Abstract: A method and apparatus for estimating a carrier frequency offset (CFO) in a Digital Radio Mondiale receiver is provided. Orthogonal frequency-division multiplexing (OFDM) demodulation is performed on a received DRM signal to produce OFDM symbols. A cell characteristic in corresponding cells in the OFDM symbols is compared and a carrier index of a frequency pilot cell in the cells is identified based upon the compared cell characteristic. The CFO is estimated based on the identified carrier index of the frequency pilot cell. The ratio of values of the cell characteristic in corresponding cells may be calculated and the frequency pilot cell identified by identifying cells for which the cell characteristic is most nearly equal. The CFO may be estimated by comparing the identified carrier index with an expected carrier index of a frequency pilot cell.

Abstract translation: 提供了一种用于估计数字无线电广播接收机中的载波频率偏移（CFO）的方法和装置。 对接收到的DRM信号进行正交频分复用（OFDM）解调以产生OFDM符号。 比较OFDM符号中的相应小区中的小区特性，并且基于比较的小区特性来识别小区中的频率导频小区的载波索引。 基于识别的频率导频小区的载波指数来估计CFO。 可以计算相应小区中的小区特性的值的比率，并且通过识别小区特性最接近相等的小区来识别频率导频小区。 可以通过将所识别的载波索引与频率导频小区的预期载波索引进行比较来估计CFO。