公开(公告)号：US07795131B2

公开(公告)日：2010-09-14

申请号：US11684646

申请日：2007-03-12

Applicant: Kuan-Jui Huang ,  Jie-Mei Huang ,  Chung-Hsiang Wang

Inventor： Kuan-Jui Huang ,  Jie-Mei Huang ,  Chung-Hsiang Wang

IPC: H01L21/4763

CPC classification number: H01L21/76885

Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.

Abstract translation: 一种制造金属互连的方法及其金属间介电层。 通过电镀工艺在衬底上形成设置在其上的第一金属互连图案和第二金属互连图案。 随后，在衬底，第一金属互连图案和第二金属互连图案上形成金属间介电层。 然后将金属间介电层平坦化，并暴露第二金属互连图案。

公开(公告)号：US07674392B2

公开(公告)日：2010-03-09

申请号：US11557110

申请日：2006-11-07

Applicant: Hsien-Lung Ho

Inventor： Hsien-Lung Ho

IPC: C03C15/00

CPC classification number: B81C1/00142

Abstract: The present invention provides a method of fabricating a hinge. First, a wafer is provided, and a hinge region and at least two through regions are defined on the wafer. The wafer in the hinge region is partially removed from a bottom surface of the wafer. Subsequently, the wafer in the through regions is completely removed from a top surface of the wafer, and the hinge is formed. Thereafter, a wafer level test is performed on the hinge of the wafer. Next, an etching process is performed to adjust the shape of the hinge. According to the method of the present invention, the thickness of the hinge is no longer limited by the thickness of the wafer, and the hinge can accept the wafer level test.

Abstract translation: 本发明提供一种制造铰链的方法。 首先，提供晶片，并且在晶片上限定铰链区域和至少两个贯通区域。 铰链区域中的晶片从晶片的底表面部分地移除。 随后，贯通区域中的晶片从晶片的顶表面完全去除，形成铰链。 此后，对晶片的铰链进行晶片级测试。 接下来，进行蚀刻处理以调节铰链的形状。 根据本发明的方法，铰链的厚度不再受到晶片的厚度的限制，铰链可以接受晶圆级测试。

公开(公告)号：US07432208B2

公开(公告)日：2008-10-07

申请号：US11461768

申请日：2006-08-01

Applicant: Yu-Fu Kang

Inventor： Yu-Fu Kang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: B81C1/0015

Abstract: A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate and the sacrificial layer, the second photoresist pattern exposing a part of the substrate and the sacrificial layer, forming a structure layer on the substrate, the second photoresist pattern, and the sacrificial layer, performing a lift off process to remove the second photoresist pattern and the structure layer above the second photoresist pattern, and performing a dry etching process to remove the sacrificial layer in order to make the structure layer become the suspension structure.

Abstract translation: 一种制造悬架结构的方法，包括提供基板，在基板上形成第一光致抗蚀剂图案，加热第一光致抗蚀剂图案以硬化其作为牺牲层，在基板和牺牲层上形成第二光致抗蚀剂图案，第二光致抗蚀剂 在衬底，第二光致抗蚀剂图案和牺牲层上形成结构层，执行剥离工艺以除去第二光致抗蚀剂图案和第二光致抗蚀剂图案之上的结构层的图案，暴露衬底和牺牲层的一部分 ，并且进行干蚀刻工艺以去除牺牲层，以使结构层变成悬浮结构。

公开(公告)号：US07413963B2

公开(公告)日：2008-08-19

申请号：US11279561

申请日：2006-04-12

Applicant: Shih-Min Huang ,  Sh-Pei Yang

Inventor： Shih-Min Huang ,  Sh-Pei Yang

IPC: H01L21/00 ,  H01L21/44

CPC classification number: G03F7/168 ,  H01L21/6708 ,  Y10S438/947

Abstract: A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding the central region on the surface of the wafer. Subsequently, the coating material layer positioned in the bevel region is removed according to the reference pattern.

Abstract translation: 边缘斜面冲洗的方法。 首先，提供其上设置有涂层层的晶片。 将光束光学投影在晶片上以形成参考图案。 参考图案限定了中心区域和围绕晶片表面上的中心区域的斜面区域。 随后，根据参考图案去除位于斜面区域中的涂层层。

公开(公告)号：US07297610B2

公开(公告)日：2007-11-20

申请号：US11160975

申请日：2005-07-18

Applicant: Chen-Hsiung Yang

Inventor： Chen-Hsiung Yang

IPC: H01L21/30

CPC classification number: H01L21/78

Abstract: First, a device wafer having a substrate layer and a device layer is provided. Then, a first mask pattern is utilized to remove the device layer uncovered by the first mask pattern. Subsequently, a medium layer is formed on the surface of the device wafer, and the medium layer is then bonded to a carrier wafer. Thereafter, a second mask pattern is utilized to remove the substrate layer uncovered by the second mask pattern. Finally, the medium layer is separated from the carrier wafer, the substrate layer is bonded to an extendable film, and the medium layer is then removed.

Abstract translation: 首先，提供具有基板层和器件层的器件晶片。 然后，使用第一掩模图案来去除由第一掩模图案未覆盖的器件层。 随后，在器件晶片的表面上形成介质层，然后将介质层接合到载体晶片。 此后，利用第二掩模图案来去除未被第二掩模图案覆盖的基底层。 最后，将介质层与载体晶片分离，将基底层粘合到可延伸的膜上，然后除去介质层。

公开(公告)号：US07262078B2

公开(公告)日：2007-08-28

申请号：US10906972

申请日：2005-03-15

Applicant: Wei-Shun Lai ,  Shu-Hua Hu ,  Kuan-Jui Huang ,  Chin-Chang Pan ,  Yuan-Chin Hsu

Inventor： Wei-Shun Lai ,  Shu-Hua Hu ,  Kuan-Jui Huang ,  Chin-Chang Pan ,  Yuan-Chin Hsu

IPC: H01L21/44

CPC classification number: B81C1/00365 ,  B81C2201/0132 ,  B81C2201/018 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.

Abstract translation: 提供基板。 衬底包括设置在衬底中的多个器件，设置在衬底的表面上并电连接到器件的多个接触焊盘以及位于衬底表面上的表面电介质层。 此后，进行至少包括等离子体蚀刻工艺的表面处理工艺。 随后，至少进行等离子体增强化学气相沉积（PECVD）工艺以在表面电介质层上形成电介质层。 以高频/低频交替方式执行PECVD处理。 接着，形成电介质层上的掩模图案，进行各向异性蚀刻处理，以形成对应于电介质层中的接触焊盘的多个开口。 这些开口暴露接触垫，并且每个开口具有向外倾斜的侧壁。

公开(公告)号：US07256128B2

公开(公告)日：2007-08-14

申请号：US10711883

申请日：2004-10-12

Applicant: Chen-Hsiung Yang

Inventor： Chen-Hsiung Yang

IPC: H01L21/311

CPC classification number: B81C1/00571

Abstract: A wafer, having at least a spindle region and at least two through regions alongside the spindle region, is provided. The wafer in the spindle region is partially removed from the bottom surface. Thereafter, the bottom surface is bonded to a carrier with a bonding layer, and the wafer in the through regions is completely removed from the top surface.

Abstract translation: 提供了具有至少一个主轴区域和沿主轴区域的至少两个贯通区域的晶片。 主轴区域中的晶片从底表面部分地移除。 此后，底面通过接合层与载体接合，贯通区域的晶片从顶面完全除去。

公开(公告)号：US07045463B2

公开(公告)日：2006-05-16

申请号：US10904188

申请日：2004-10-28

Applicant: Chen-Hsiung Yang

Inventor： Chen-Hsiung Yang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: B81C1/00587

Abstract: A method of etching cavities having different aspect ratios. An etching stop layer is formed on the bottom surface of a substrate, and a mask pattern is formed on the top surface of the substrate. The mask pattern includes a plurality of sacrificial patterns positioned on both a first cavity predetermined region and a second cavity predetermined region. Then, an etching process is performed to remove the substrate not covered by the mask layer. Then, the etching stop layer is removed, as well as the sacrificial patterns and the substrate covered by the sacrificial patterns.

Abstract translation: 蚀刻具有不同纵横比的腔的方法。 在基板的底面形成有蚀刻停止层，在基板的上表面形成有掩模图案。 掩模图案包括定位在第一空腔预定区域和第二空腔预定区域两者上的多个牺牲图案。 然后，进行蚀刻处理以去除未被掩模层覆盖的衬底。 然后，去除蚀刻停止层，以及由牺牲图案覆盖的牺牲图案和基板。

公开(公告)号：US07566574B2

公开(公告)日：2009-07-28

申请号：US11850678

申请日：2007-09-06

Applicant: Chen-Hsiung Yang

Inventor： Chen-Hsiung Yang

IPC: H01L21/00

CPC classification number: H01L21/2007 ,  B81B2203/0127 ,  B81C1/00603 ,  B81C2201/019

Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.

Abstract translation: 提供了一种执行双面处理的方法。 首先，提供具有布置在前表面上的结构图案的晶片。 接着，在结构图案上限定多个前划线，并将填充层填充到前划线中。 接着，用结合层将结构图形结合到载体晶片上，并且在晶片的背面形成多个后划线。 最后，去除填充在前划痕线中的填充层。

公开(公告)号：US07505118B2

公开(公告)日：2009-03-17

申请号：US10711882

申请日：2004-10-12

Applicant: Chen-Hsiung Yang

Inventor： Chen-Hsiung Yang

IPC: G03B27/58 ,  H01L21/683

CPC classification number: G03F7/70691 ,  G03F7/70425 ,  G03F7/70708 ,  G03F9/7003

Abstract: A wafer carrier for carrying a wafer includes a transparent base and a conducting layer. The transparent base has dimensions similar to that of the wafer, and bonds the wafer with a bonding layer. The conducting layer is transparent, and can be attracted by an electrostatic chuck so that the electrostatic chuck can deliver the wafer.

Abstract translation: 用于承载晶片的晶片载体包括透明基底和导电层。 透明基底具有与晶片相似的尺寸，并且用晶片结合层。 导电层是透明的，并且可以被静电吸盘吸引，使得静电卡盘可以输送晶片。