公开(公告)号：US10063138B1

公开(公告)日：2018-08-28

申请号：US15428726

申请日：2017-02-09

Applicant: Transphorm Inc.

Inventor： Liang Zhou ,  Yifeng Wu

IPC: H02M1/42

CPC classification number: H02M1/4208 ,  G01R19/0084 ,  G01R19/0092 ,  H02M1/4233 ,  H02M7/219 ,  Y02B70/126 ,  Y02P80/112

Abstract: A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.

公开(公告)号：US10043896B2

公开(公告)日：2018-08-07

申请号：US15836157

申请日：2017-12-08

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/15 ,  H01L29/04 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51

Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

公开(公告)号：US09634100B2

公开(公告)日：2017-04-25

申请号：US14934565

申请日：2015-11-06

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Srabanti Chowdhury ,  Ilan Ben-Yaacov

IPC: H01L31/0328 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/207 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7786 ,  H01L29/78

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

公开(公告)号：US09590494B1

公开(公告)日：2017-03-07

申请号：US14802333

申请日：2015-07-17

Applicant: Transphorm Inc.

Inventor： Liang Zhou ,  Yifeng Wu

IPC: H02M7/06 ,  H02M1/42 ,  H02M7/217 ,  G01R1/20 ,  G01R19/00

CPC classification number: H02M1/4208 ,  G01R1/203 ,  G01R19/0092 ,  H02M1/4233 ,  H02M7/219 ,  Y02B70/126

Abstract: A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.

Abstract translation: 功率因数校正电路包括耦合到第一参考地的一对基于III-N的开关和与电流感测电阻器串联连接的电感元件。 电流感测电阻器的第一侧耦合到与第一参考地电隔离的第二参考地，并且电流感测电阻器的第二侧耦合到控制电路。 控制电路还耦合到第二参考地，并且被配置为在功率因数校正电路的操作期间测量流过电感元件的电流。

公开(公告)号：US09443938B2

公开(公告)日：2016-09-13

申请号：US14327371

申请日：2014-07-09

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L29/7783 ,  H01L29/045 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/51 ,  H01L29/66462

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract translation: 晶体管包括III-N层结构，其包含在III-N势垒层和p型III-N层之间的III-N沟道层。 晶体管还包括源极和漏极之间的源极，漏极和栅极，栅极在III-N层结构之上。 p型III-N层包括至少部分地在栅极和漏极之间的器件访问区域中的第一部分，并且p型III-N层的第一部分电连接到源极和电 从排水沟隔离。 当晶体管偏置为截止状态时，p型层可能导致器件访问区域中的沟道电荷随漏极电压增加而消耗，从而导致更高的击穿电压。

公开(公告)号：US09362903B2

公开(公告)日：2016-06-07

申请号：US14708627

申请日：2015-05-11

Applicant: Transphorm Inc.

Inventor： Yifeng Wu ,  Liang Zhou ,  Zhan Wang

IPC: H03K3/00 ,  H03K17/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28 ,  H01L29/66 ,  H03K17/687

CPC classification number: H03K17/162 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/66522 ,  H01L29/7786 ,  H03K17/163 ,  H03K2017/6875

Abstract: An electronic component includes a switching device comprising a source, a gate, and a drain, the switching device having a predetermined device switching rate. The electronic component further includes a gate driver electrically connected to the gate and coupled between the source and the gate of the switching device, the gate driver configured to switch a gate voltage of the switching device at a gate driver switching rate. The gate driver is configured such that in operation, an output current of the gate driver cannot exceed a first current level, wherein the first current level is sufficiently small to provide a switching rate of the switching device in operation to be less than the predetermined device switching rate.

公开(公告)号：US09293561B2

公开(公告)日：2016-03-22

申请号：US14262649

申请日：2014-04-25

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Lee McCarthy ,  Nicholas Fichtenbaum

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L29/207

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/02581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/7787

Abstract: A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.

Abstract translation: 描述了III-N器件具有缓冲层，缓冲层上的第一III-N材料层，与缓冲层相反侧的第一III-N材料层上的第二III-N材料层和分散体 缓冲层和通道层之间的阻挡层。 第一III-N材料层是沟道层，并且第一III-N材料层和第二III-N材料层之间的组成差异在第一III-N材料层中诱导2DEG沟道。 在沟道层和分散阻挡层的界面处的负电荷的片材或分布限制电子远离缓冲层。

公开(公告)号：US09293458B2

公开(公告)日：2016-03-22

申请号：US14058089

申请日：2013-10-18

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  James Honea ,  Carl C. Blake, Jr. ,  Robert Coffie ,  Yifeng Wu ,  Umesh Mishra

IPC: H03K17/687 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06 ,  H03K17/567 ,  H01L23/495 ,  H01L25/16 ,  H01L23/64 ,  H01L25/18

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/647 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0605 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract translation: 电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。 高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线 单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线 并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

公开(公告)号：US09224721B2

公开(公告)日：2015-12-29

申请号：US14585705

申请日：2014-12-30

Applicant: Transphorm Inc.

Inventor： Yifeng Wu

IPC: H01L25/00 ,  H01L25/16 ,  H01L25/07 ,  H05K1/02 ,  H03K17/16 ,  H01L23/12 ,  H01L23/367 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78 ,  H01L23/552 ,  H01L23/64

CPC classification number: H01L25/50 ,  H01L23/12 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/552 ,  H01L23/642 ,  H01L25/074 ,  H01L25/117 ,  H01L25/16 ,  H01L25/165 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/7827 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2924/30107 ,  H03K17/164 ,  H03K2217/0045 ,  H05K1/0218 ,  H05K1/0263 ,  H05K1/162 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract translation: 描述了一种电子部件，其包括封装在第一封装中的第一晶体管，第一晶体管安装在第一封装的第一导电部分上，以及封装在第二封装中的第二晶体管，第二晶体管安装在第二导电 第二包装的部分。 所述部件还包括在第一金属层和第二金属层之间包括绝缘层的基板。 所述第一封装在所述基板的一侧，所述第一导电部分与所述第一金属层电连接，所述第二封装在所述基板的另一侧，所述第二导电部分与所述第二金属层电连接。 第一封装与第二封装相对，第一导电部分的第一区域的至少50％与第二导电部分的第二区域相对。

公开(公告)号：US09224671B2

公开(公告)日：2015-12-29

申请号：US14522154

申请日：2014-10-23

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  Yuvaraj Dora ,  Yifeng Wu ,  Umesh Mishra ,  Nicholas Fichtenbaum ,  Rakesh K. Lal

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L21/18 ,  H01L23/34 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L29/30 ,  H01L23/373

CPC classification number: H01L23/34 ,  H01L21/02118 ,  H01L21/0254 ,  H01L21/486 ,  H01L21/76254 ,  H01L23/3732 ,  H01L23/3738 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract translation: III-N器件用III-N层，其上的电极，与III-N层和电极相邻的钝化层，与钝化层和电极相邻的厚绝缘层，能够转移大量的高导热载体 远离III-N器件的热量，以及厚绝缘层和载体之间的结合层。 接合层将厚绝缘层附着到载体上。 厚的绝缘层可以具有精确控制的厚度并且是导热的。