Abstract:
A method, computer program product and system of minimizing epigenetic surprisal data, for analysis or transmission over a network processing system, either by comparing epigenetic surprisal data to a fixed baseline epigenetic data, so that all of the comparisons were made to the same baseline epigenetic data, or by comparing epigenetic surprisal data to a rolling baseline of epigenetic surprisal data - that is, after each comparison the baseline is changed to the data from the time point which had been compared previously.
Abstract:
Multiple sets of character data having termination characters are compared using parallel processing and without causing unwarranted exceptions. Each set of character data to be compared is loaded within one or more vector registers. In particular, in one embodiment, for each set of character data to be compared, an instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. Further, an instruction is used to find the index of the first delimiter character, i.e., the first zero or null character, or the index of unequal characters. Using these instructions, a location of the end of one of the sets of data or a location of an unequal character is efficiently provided.
Abstract:
Inadvertent data swaps can be prevented by measuring volume of transactions in distributed computing environment to determine locations for potential data swaps; and managing a correlation between a thread identification (ID) and transaction header (ID) for transactions in the distributed computing environment. In some embodiments, the prevention of data swaps can further include performing a data transmission interruption to avoid data swaps at the locations for potential data swaps. When the thread identification (ID) and transaction header (ID) do not match the potential for data swaps can be high.
Abstract:
A buried power rail contact structure is provided that wraps around a source/drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height as compared to a height of a neighboring source/drain contact structure that contacts a surface of a source/drain region of a second FET. Both the buried power rail contact structure and the source/drain contact structure have a negative taper, i.e., each of the buried power rail contact structure and the source/drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommostsurface of the contact structure. Such contact structures reduce the parasitic capacitance between a functional gate structure and the contact structure.
Abstract:
Automatic measurement of semantic textual similarity of conversations, by: receiving two conversation texts, each comprising a sequence of utterances; encoding each of the sequences of utterances into a corresponding sequence of semantic representations; computing a minimal edit distance between the sequences of semantic representations; and, based on the computation of the minimal edit distance, performing at least one of: quantifying a semantic similarity between the two conversation texts, and outputting an alignment of the two sequences of utterances with each other.
Abstract:
A system for synchronizing and maintaining audited code and toolchain access in a modern software development pipeline are present. In particular, by leveraging software bots to monitor changes in a development team's preferred access control mechanism, such changes in the perferred state can be stored as perferred/target configuration in a source controlled repository. Further, the same (or other) software bots may be used to monitor for configuration drift between the source-controlled system and the preferred/ target configuration stored in the repository and eliminate drifts automatically if possible or alert interested parties about those drifts.
Abstract:
Techniques for performing analog-to-digital conversion are disclosed. For example, a method performs an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.
Abstract:
A system, method, and computer program product for implementing deep learning software model modification is provided. The method includes monitoring operational performance of a software model. An expected confidence level associated with the operational performance is first determined and it is determined that an inference associated with the expected confidence level is below a selected range of inferences associated with assigning new feature data as candidate video data. A candidate sequence comprising video data associated with the candidate video data is received and a similarity between frames of the candidate sequence is determined. A frame comprising a highest similarity with respect to segments of candidate video data is selected and it is detected that the frame is not associated with additional frames stored within a full cache structure. The software model is retrained such that the operational performance is modified.
Abstract:
An application configuration tool and associated method for supporting deployment of an application on a server that has a set of configurations available for applications deployed on the server. The method attempts to match every configuration required by the application to a configuration available on the server. In case of multiple candidates that match, one is selected. When there is no match an error message is generated. The method is iterated to inspect each selected configuration to identify any references contained in the selected configuration that themselves need further configurations. The iteration of inspecting and the matching to follow the references is continued until all such references are exhausted either by matching or failure to match and consequent error message generation. Finally, a configuration report is output specifying the selected configurations and, to the extent that not all required configurations have been matched to available configurations, the error messages.
Abstract:
Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.