LOOKASIDE CACHE A "lookaside" cache architecture whereby the cache system is situated on the processor bus in parallel with the memory controller. This design enables the cache system and the memory controller to begin servicing a processor memory read request simultaneously, thereby removing any delay penalty for cache misses that would otherwise occur in a traditional look-through design. The cache and the memory controller both begin a processor memory read cycle simultaneously. If a cache miss occurs, the memory controller completes the cycle. If a cache hit occurs, the cache system aborts the memory controller and completes the memory read cycles in zero wait states. The lookaside cache design allows the cache system to be easily removable from the computer system to provide an optional capability.