公开(公告)号：AT204996T

公开(公告)日：2001-09-15

申请号：AT94301988

申请日：1994-03-21

Applicant: COMPAQ COMPUTER CORP

Inventor： THOME GARY W ,  COLLINS MICHAEL J

IPC: G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00 ,  G06F13/28

Abstract: Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

公开(公告)号：DE69427421D1

公开(公告)日：2001-07-19

申请号：DE69427421

申请日：1994-03-22

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  SANTELER PAUL A ,  THOME GARY W ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：AT202227T

公开(公告)日：2001-06-15

申请号：AT94302014

申请日：1994-03-22

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  SANTELER PAUL A ,  THOME GARY W ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：DE69127773T2

公开(公告)日：1998-04-02

申请号：DE69127773

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： COLLINS MICHAEL J ,  TIPLEY ROGER E

IPC: G06F12/08 ,  G06F12/12

Abstract: An apparatus for performing LRU techniques for a 4 way set associative cache system. A RAM stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LRU way information values. Processor or snoop operation is determined and the way use aging information valued is based on snooping or processor operations. For processor operations the accessed or to be accessed way is set as the MRU, while in snoop operations, the way being accessed is set as the LRU. The aging of the remaining ways is shuffled accordingly. This shuffling occurs each cycle but is only stored on processor cache hit, processor read cache miss and snoop hit operations.

公开(公告)号：AT158882T

公开(公告)日：1997-10-15

申请号：AT91305419

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： COLLINS MICHAEL J ,  TIPLEY ROGER E

IPC: G06F12/08 ,  G06F12/12

Abstract: An apparatus for performing LRU techniques for a 4 way set associative cache system. A RAM stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LRU way information values. Processor or snoop operation is determined and the way use aging information valued is based on snooping or processor operations. For processor operations the accessed or to be accessed way is set as the MRU, while in snoop operations, the way being accessed is set as the LRU. The aging of the remaining ways is shuffled accordingly. This shuffling occurs each cycle but is only stored on processor cache hit, processor read cache miss and snoop hit operations.

公开(公告)号：CA2044472A1

公开(公告)日：1991-12-16

申请号：CA2044472

申请日：1991-06-13

Applicant: COMPAQ COMPUTER CORP

Inventor： KELLY PHILIP C ,  COLLINS MICHAEL J

IPC: G06F12/02

Abstract: MEMORY ADDRESS SPACE DETERMINATION USING PROGRAMMABLE LIMIT REGISTERS WITH SINGLE-ENDED COMPARATORS An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

公开(公告)号：DE69428071D1

公开(公告)日：2001-10-04

申请号：DE69428071

申请日：1994-03-21

Applicant: COMPAQ COMPUTER CORP

Inventor： THOME GARY W ,  COLLINS MICHAEL J

IPC: G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00 ,  G06F13/28

Abstract: Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

公开(公告)号：DE69131610D1

公开(公告)日：1999-10-21

申请号：DE69131610

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： KELLEY PHILIP CO ,  COLLINS MICHAEL J

IPC: G06F12/06 ,  G06F12/08

Abstract: An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

公开(公告)号：AT184714T

公开(公告)日：1999-10-15

申请号：AT91305420

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： KELLEY PHILIP CO ,  COLLINS MICHAEL J

IPC: G06F12/06 ,  G06F12/08

Abstract: An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

公开(公告)号：DE69427421T2

公开(公告)日：2001-11-15

申请号：DE69427421

申请日：1994-03-22

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  SANTELER PAUL A ,  THOME GARY W ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.