The invention provides a debug clock domain circuit of an SOC chip.The debug clock domain circuit comprises four clock domains, namely a super-speed CPU system, a high-speed debug system, an intermediate-speed system and a low-speed debug system; the super-speed CPU system comprises a multi-core CPU and cache circuit, and the running frequency is highest in the whole chip; the high-speed debug system is responsible for exporting a large quantity of debug data in real time in the high-speed running process of the CPU; the intermediate-speed system is a main bus and an external device control circuit in the chip; the low-speed debug system is mainly responsible for configuration in the debug process; signal connections between the clock domains are all realized through asynchronous bridges located on the boundaries of the clock domains.