The invention discloses a memory array. The memory array comprises a plurality of two-tube memory units, a plurality of mutually paralleling bit lines, and a plurality of mutual-insulation word lines vertical to the bit lines, two memory tubes which are adjacent up and down of the whole memory array share a source end or a leakage end in a back-to-back manner, a row of left and right adjacent memory tubes share a grid electrode, the grid electrodes of the memory tubes are connected with the memory tube word lines, the whole memory array shares a P trap, the bit lines in a longitudinal same column direction are connected, and different columns of the bit lines of the memory units are respectively externally connected; the word lines in a transverse same row are connected, memory word lines are respectively externally connected, all selection tube word lines in all odd number rows are connected, and all selection tube word lines in all even number lines are connected; and all source ends are connected in a back-to-back manner, and all transverse source lines are respectively externally connected. The memory array can reduce electric leakage of unselected rows in the read operation, and can accelerate the reading speed.