A power transistor bias circuit is provided, and relates to the field of electronic technologies, so as to reduce impact of a switch action of a power transistor on a bias voltage of the power transistor, and improve stability of a control loop and reliability of the power transistor. A specific solution is that: the power transistor bias circuit includes: a first P-type field effect transistor (21), a second P-type field effect transistor (22), a P-type field effect transistor driver module (23), a first voltage stabilization capacitor (24), a first bias module (25), a first N-type field effect transistor (31), a second N-type field effect transistor (32), an N-type field effect transistor driver module (33), a second voltage stabilization capacitor (34), a second bias module (35), and a PWM controller (41). The first bias module (25) obtains and outputs a first bias voltage based on a voltage reference, a preset coefficient, and a power voltage of a PVDD. The second bias module (35) obtains and outputs a second bias voltage based on the voltage reference, the preset coefficient, and a power ground voltage of a PGND. A voltage difference between the power voltage of the PVDD and the first bias voltage is equal to a voltage difference between the second bias voltage and the power ground voltage of the PGND.