The present application relates to the technical field of chip packaging. Provided are a packaged chip and a packaging method. The packaged chip comprises a printed circuit board, a chip provided on the upper surface of the printed circuit board, and a packaging encapsulant provided on the surface of the printed circuit board and used for packaging the chip. First solder balls are provided on the lower surface of the printed circuit board and at positions corresponding to the packaging encapsulant. The chip is fixed on the printed circuit board via second solder balls. A via is provided on the printed circuit board. The via is arranged below the chip. In the present application, the via is provided on the printed circuit board at a position corresponding to the chip, during secondary SMT, air between the chip and the printed circuit board is expelled through the via, thus preventing the phenomenon of the second solder balls bursting or the printed circuit board bulging, and increasing the yield of the packaged chip.