A technology for a memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can apply a first voltage level to a selected wordline associated with the plurality of memory cells during a body reset operation. The memory controller can apply a second voltage level to an unselected wordline associated with the plurality of memory cells during the body reset operation. The selected wordline can transit to a stable negative pillar potential, such that selected memory cells associated with the selected wordline can have reduced threshold voltage instability.