Invention Publication
EP0847089A1 Method and device for suppressing parasitic effects in a junction-insulated integrated circuit
失效
装置和方法,用于抑制在集成电路中具有的pn绝缘区的寄生效应
- Patent Title: Method and device for suppressing parasitic effects in a junction-insulated integrated circuit
- Patent Title (中): 装置和方法,用于抑制在集成电路中具有的pn绝缘区的寄生效应
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Application No.: EP96830614.2Application Date: 1996-12-09
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Publication No.: EP0847089A1Publication Date: 1998-06-10
- Inventor: Ravanelli, Enrico Maria , Pozzoni, Massimo , Pedrazzini, Giorgio , Ricotti, Giulio
- Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.
- Applicant Address: Via C. Olivetti, 2 20041 Agrate Brianza (Milano) IT
- Assignee: SGS-THOMSON MICROELECTRONICS s.r.l.
- Current Assignee: SGS-THOMSON MICROELECTRONICS s.r.l.
- Current Assignee Address: Via C. Olivetti, 2 20041 Agrate Brianza (Milano) IT
- Agency: Maggioni, Claudio
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L27/02
Abstract:
The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.
Public/Granted literature
- EP0847089B1 Method and device for suppressing parasitic effects in a junction-insulated integrated circuit Public/Granted day:2002-10-23
Information query
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