公开(公告)号：EP0757444A1

公开(公告)日：1997-02-05

申请号：EP95830342.2

申请日：1995-07-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ricotti, Giulio ,  Bardelli, Roberto ,  Rossi, Domenico

IPC: H03K17/687 ,  G06K7/08 ,  G06K19/07

CPC classification number: H03K17/6874

Abstract: The switch in accordance with the present invention comprises two MOS transistors (M1,M2) whose main conduction paths are connected respectively upstream and downstream of the terminals (T1,T2) of the network (C2) of which it is desired to control electrically the electrical connection. In this manner current can flow in the network (C2) only if both the transistors (M1,M2) are conducting.

Abstract translation: 用在本发明中雅舞蹈所述开关包括两个MOS晶体管（M1，M2），其主传导路径分别连接上游和其中的期望来控制电的所述网络（C2）的端子（T1，T2）的下游 电气连接。 以这种方式电流可以在网络（C2）流入只有当这两个晶体管（M1，M2）导通。

公开(公告)号：EP0751622A1

公开(公告)日：1997-01-02

申请号：EP95830277.0

申请日：1995-06-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ricotti, Giulio ,  Bardelli, Roberto ,  Rossi, Domenico

IPC: H03K17/687 ,  G06K19/07

CPC classification number: H03K17/6874 ,  G06K19/0723 ,  H03K17/6872

Abstract: The switch of this invention has two conduction terminals (TA,TB) and basically consists of the parallel coupling, across the two conduction terminals (TA,TB), of a first N-channel MOS transistor (M1L) and second P-channel MOS transistor (M1R). The first MOS transistor will be conducting when the signal applied to the conduction terminals has a first polarity, and the second MOS transistor will be conducting when the signal applied to the conduction terminals has a second polarity.
Advantageously, if two unidirectional conduction circuit elements (D1L,D1R) are respectively connected in series with the main conduction paths of the two MOS transistors (M1L,M1R), the drain/body junctions (DI1L,DI1R) of the latter will never be conducting regardless of the way the switch is connected.

Abstract translation: 本发明的开关具有两个导通端子（TA，TB），并且基本上由穿过第一N沟道MOS晶体管（M1L）和第二P沟道MOS（M1L）的两个导通端子（TA，TB）的并联耦合 晶体管（M1R）。 当施加到导电端子的信号具有第一极性时，第一MOS晶体管将导通，并且当施加到导电端子的信号具有第二极性时，第二MOS晶体管将导通。 有利的是，如果两个单向导通电路元件（D1L，D1R）分别与两个MOS晶体管（M1L，M1R）的主导通路径串联连接，则后者的漏极/本体接头（DI1L，DI1R）将永远不会 无论开关的连接方式如何，都要进行。

公开(公告)号：EP0658835A1

公开(公告)日：1995-06-21

申请号：EP93830512.5

申请日：1993-12-17

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ricotti, Giulio ,  Rossi, Domenico

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: A voltage, replica of the difference between two dissimilar base-emitter voltages in the form of an intrinsic input offset voltage of a differential input pair of transistors of a noninverting, buffer-configured operational amplifier, is summed with a pre-established fraction of a base-emitter voltage, to produce a voltage reference without thermal drift of a level that can be as low as few 10mV. The intrinsic input offset voltage is controlled by a local feedback loop acting on the bias current that is forced through the input pair of transistors that may be realized with a certain area ratio. The relatively simple circuit is useful in battery operated, low supply voltage, systems.

Abstract translation: 不同反相缓冲器配置的运算放大器的差分输入输入对晶体管的本征输入失调电压形式的两个不同的基极 - 发射极之间的差异的电压的复制品与预先确定的 基极 - 发射极电压，产生无电热漂移的电压基准，电平可低至10mV。 本征输入失调电压由作用在偏置电流上的局部反馈回路控制，该偏置电流被迫通过输入的一对晶体管，该晶体管可以以一定面积比实现。 相对简单的电路在电池供电，低电压，系统中是有用的。

公开(公告)号：EP0847089A1

公开(公告)日：1998-06-10

申请号：EP96830614.2

申请日：1996-12-09

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ravanelli, Enrico Maria ,  Pozzoni, Massimo ,  Pedrazzini, Giorgio ,  Ricotti, Giulio

IPC: H01L27/088 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/088

Abstract: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.

Abstract translation: 所描述的方法被施加到与形成于具有n型材料中的至少一个区域（11），且结绝缘，第一电接触装置（20,21）上的头的p型材料的基片（10）的集成电路 在n型区域（11）和第三电接触装置的基板，第二电接触器件（14,14“）的表面（8）上连接到所述集成电路的基准（接地）端子的基板的背面 ， 为了避免在基片的电流由于寄生双极晶体管的集成电路中，所述方法提供了用于监测所述第二接触装置（14,14“）的电势的某些操作条件的导通来检测，如果该电势从出发（ 地）通过在量高于预定阈值的参考端子的电势。 如果发生此第一接触装置（20,21）被带到第二接触装置（14,14“）的电位，否则，这些都在参考端子的（接地）电势保持。 因此，一个装置和集成电路，其利用该方法进行了描述。