An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.