公开(公告)号：DE3166256D1

公开(公告)日：1984-10-31

申请号：DE3166256

申请日：1981-03-23

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BAZLEN DIETER DR ,  HAJDU JOHANN ,  KNAUFT GUNTER

IPC: G06F7/00 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G06F7/48 ,  G06F9/38

Abstract: The cycle time of a data processing system should always be determined in such a manner that data from a source register, after having been propagated through, if necessary, several transfer sections and line drivers, and through a chain of logic circuits for the respective processing steps, can be stored in the result or sink register safely and even with the worst case propagation tolerance of all elements involved. The ideal cycle time therefore, which is dependent on the processing speed of the slowest chain of logic circuits, has to have added time segments for the worst case of unprecise clocking. A reduction of the cycle time by the above mentioned added time segments, and if necessary by the propagation delays in the transfer sections and in the line drivers, is achieved when the chain of logic circuits and thus its delay time is divided into two partial chains with the partial delays and if the sink register is arranged between the two partial chains. By thus splitting the chain of logic circuits into two partial chains, the logic partial functions can be executed during that time segment which is composed of the above mentioned added time segments.

公开(公告)号：CA1191615A

公开(公告)日：1985-08-06

申请号：CA429597

申请日：1983-06-03

Applicant: IBM

Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  RAETH FRANZ J

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318

Abstract: ARRANGEMENT IN THE INSTRUCTION UNIT OF A MICROPROGRAM-CONTROLLED PROCESSOR FOR THE DIRECT HARDWARE-CONTROLLED EXECUTION OF PARTICULAR INSTRUCTIONS In a microprogram-controlled processor, having an additional operating mode in which particular functions can be executed under direct hardware control, a mode latch is provided signalizing the instruction decoder whether micro program instructions or directly controlled macro instructions are to be executed. The microprogram instructions are executed in the usual manner. For the execution of the directly controlled macro instructions, the control storage of the processor is not required for supplying micro instructions. Instead, this storage with the operation decoder as an address supplies one or several hardware control words. The hardware control words consist of individual control bits, each of which directly controls one hardware function.

公开(公告)号：DE2842750A1

公开(公告)日：1980-04-10

申请号：DE2842750

申请日：1978-09-30

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C19/00

Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

公开(公告)号：CA994873A

公开(公告)日：1976-08-10

申请号：CA225410

申请日：1975-04-22

Applicant: IBM

Inventor： GENG HELLMUTH ,  HAJDU JOHANN ,  SKUIN PETAR

公开(公告)号：CA971637A

公开(公告)日：1975-07-22

申请号：CA154489

申请日：1972-10-17

Applicant: IBM

Inventor： GENG HELLMUTH ,  HAJDU JOHANN ,  SKUIN PETAR

公开(公告)号：CA958488A

公开(公告)日：1974-11-26

申请号：CA146796

申请日：1972-07-11

Applicant: IBM

Inventor： GENG HELLMUTH R ,  GOETZE VOLKMAR ,  HAJDU JOHANN ,  SKUIN PETAR

IPC: G06F11/10 ,  H03M13/05

公开(公告)号：DE2135592A1

公开(公告)日：1973-02-01

申请号：DE2135592

申请日：1971-07-16

Applicant: IBM DEUTSCHLAND

Inventor： GENG HELLMUTH R ,  HAJDU JOHANN ,  GOETZE VOLKMAR ,  SKUIN PETAR

IPC: G06F11/10 ,  H03M13/05

公开(公告)号：AU553612B2

公开(公告)日：1986-07-24

申请号：AU1530783

申请日：1983-06-02

Applicant: IBM

Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS ,  RAETH FRANZ JOSEF ,  HAJDU JOHANN

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/36

公开(公告)号：FR2406851B1

公开(公告)日：1986-04-11

申请号：FR7828926

申请日：1978-10-02

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：CA1126413A

公开(公告)日：1982-06-22

申请号：CA333041

申请日：1979-08-02

Applicant: IBM

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G06F15/20

Abstract: An LSI monolithically integrated semiconductor circuit consisting of sequential circuits and combinational circuits contains a considerable number of storage elements designed as latches which for error detection are assembled into a shift register. If a sequential circuit thus built of several minimum replaceable units is error checked according to the invention no major additional process steps in the form of further terminals and connecting pins to a module representing the minimum replaceable unit will be required. As disclosed by the invention, by minor modification of the respective input circuits in the minimum replaceable units, the first two shift register stages of a respective minimum replaceable unit are first brought into their respective complementary states. Then the shift register contents are read out in a conventional manner, with the bit positions represented respectively by the first two shift registers in all minimum replaceable units being examined at the shift output for bit equality. If bit equality is found it can be concluded that the directly preceding minimum replaceable unit shows a stuck fault. After the defective minimum replaceable unit has been exchanged the stuck fault test is repeated so a to be able to isolate any other stuck faults that might precede that minimum replaceable unit.