- Patent Title: Die top, bottom parallel/serial date with test and scan circuitry
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Application No.: US15617446Application Date: 2017-06-08
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Publication No.: US10012695B2Publication Date: 2018-07-03
- Inventor: Lee D. Whetsel
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3185 ; G01R31/3177 ; G01R31/3183 ; G01R31/28
Abstract:
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
Public/Granted literature
- US20170269159A1 3D TAP & SCAN PORT ARCHITECTURES Public/Granted day:2017-09-21
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