Invention Grant
- Patent Title: Integrated circuit manufacturing process for aligning threshold voltages of transistors
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Application No.: US15611628Application Date: 2017-06-01
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Publication No.: US10037400B2Publication Date: 2018-07-31
- Inventor: Runzi Chang , Winston Lee , Peter Lee
- Applicant: Marvell World Trade Ltd.
- Applicant Address: BB St. Michael
- Assignee: MARVELL WORLD TRADE LTD.
- Current Assignee: MARVELL WORLD TRADE LTD.
- Current Assignee Address: BB St. Michael
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G06F17/50 ; G11C11/412

Abstract:
In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.
Public/Granted literature
- US20170351802A1 INTEGRATED CIRCUIT MANUFACTURING PROCESS FOR ALIGNING THRESHOLD VOLTAGES OF TRANSISTORS Public/Granted day:2017-12-07
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