公开(公告)号：US10784250B2

公开(公告)日：2020-09-22

申请号：US16372905

申请日：2019-04-02

Applicant: Marvell World Trade Ltd.

Inventor： Runzi Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H03K17/687

Abstract: The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.

公开(公告)号：US20190148236A1

公开(公告)日：2019-05-16

申请号：US16230505

申请日：2018-12-21

Applicant: Marvell World Trade Ltd.

Inventor： Runzi Chang ,  Chuan-Cheng Cheng

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L21/764 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/28035 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795

Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

公开(公告)号：US20170351802A1

公开(公告)日：2017-12-07

申请号：US15611628

申请日：2017-06-01

Applicant: Marvell World Trade Ltd.

Inventor： Runzi Chang ,  Winston Lee ,  Peter Lee

IPC: G06F17/50 ,  G11C11/412

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116

Abstract: In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.

公开(公告)号：US09490427B2

公开(公告)日：2016-11-08

申请号：US14955326

申请日：2015-12-01

Applicant: Marvell World Trade LTD.

Inventor： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Runzi Chang

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y10T29/49117

Abstract: A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.

Abstract translation: 一种包括存储单元的电阻元件和访问存储器单元的电阻元件的器件的系统。 电阻元件包括（i）第一电极和（ii）第二电极。 该装置包括（i）连接到第一触点的第一端子和（i）连接到第二触点的第二端子。 器件的第一接触和第二接触中的一个或多个分别经由第三接触连接到电阻元件的第一电极和第二电极中的一个或多个。 第三接触的尺寸从器件的第一接触和第二接触中的一个或多个减小到存储器单元的电阻元件的第一电极和第二电极中的一个或多个。

公开(公告)号：US09397218B2

公开(公告)日：2016-07-19

申请号：US14567971

申请日：2014-12-11

Applicant: Marvell World Trade Ltd.

Inventor： Chuan-Cheng Cheng ,  Runzi Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/4238 ,  H01L29/66795

Abstract: Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer; and a first contact and a second contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance.

Abstract translation: 实施例包括半导体器件，包括：栅极层，包括（i）第一部分和（ii）第二部分，其中栅极层是非线性的，使得栅极层的第一部分相对于第二部分偏移 的栅层; 以及第一接触和第二接触，其中所述栅极层的所述第一部分处于（i）距离所述第一接触的第一距离和（ii）距所述第二接触的第二距离，其中所述第一距离与所述第二接触不同 距离。

公开(公告)号：US09391045B2

公开(公告)日：2016-07-12

申请号：US14715170

申请日：2015-05-18

Applicant: Marvell World Trade Ltd.

Inventor： Albert Wu ,  Roawen Chen ,  Chung Chyung (Justin) Han ,  Shiann-Ming Liou ,  Chien-Chuan Wei ,  Runzi Chang ,  Scott Wu ,  Chuan-Cheng Cheng

IPC: H01L21/00 ,  H01L25/04 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L25/04 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83904 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20150279806A1

公开(公告)日：2015-10-01

申请号：US14715170

申请日：2015-05-18

Applicant: Marvell World Trade Ltd.

Inventor： Albert Wu ,  Roawen Chen ,  Chung Chyung (Justin) Han ,  Shiann-Ming Liou ,  Chien-Chuan Wei ,  Runzi Chang ,  Scott Wu ,  Chuan-Cheng Cheng

IPC: H01L23/00

CPC classification number: H01L25/04 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83904 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供一种方法，包括提供半导体衬底，其具有（i）第一表面和（ii）与第一表面相对设置的第二表面，在半导体衬底的第一表面中形成一个或多个通孔 一个或多个通孔最初仅通过半导体衬底的一部分而不到达第二表面，在半导体衬底的第一表面上形成电介质膜，在电介质膜上形成再分布层，再分配层电耦合 连接到所述一个或多个通孔，将一个或多个管芯耦合到所述再分布层，形成模制化合物以封装所述一个或多个管芯的至少一部分，以及使所述半导体衬底的所述第二表面凹陷以暴露所述一个或多个通孔 。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150124520A1

公开(公告)日：2015-05-07

申请号：US14594940

申请日：2015-01-12

Applicant: Marvell World Trade LTD.

Inventor： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Runzi Chang

IPC: G11C13/00

CPC classification number: H01L45/1273 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y10T29/49117

Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.

Abstract translation: 电阻随机存取存储器的单元包括（i）电阻元件和（ii）开关。 电阻元件包括（i）第一电极和（ii）第二电极。 开关包括（i）连接到第一触点的第一端子和（i）连接到第二触点的第二端子。 第二触点通过第三触点连接到电阻元件的第二电极。 第三触点具有包括与第一表面相对的第一表面和第二表面的形状。 第三接触件的形状从第一表面朝向第二表面向内变细。

公开(公告)号：US08934285B2

公开(公告)日：2015-01-13

申请号：US14050720

申请日：2013-10-10

Applicant: Marvell World Trade Ltd.

Inventor： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Runzi Chang

IPC: G11C13/00 ,  H01L45/00

CPC classification number: H01L45/1273 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y10T29/49117

Abstract: A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area.

Abstract translation: 电阻随机存取存储器的单元包括电阻元件和访问器件。 电阻元件包括（i）第一电极和（ii）第二电极。 接入设备被配置为选择和取消选择小区。 访问装置包括（i）连接到第一触点的第一端子和（i）连接到第二触点的第二端子。 第二触点通过第三触点连接到电阻元件的第二电极。 第三触点包括（i）与第二触点接触的第一表面和（ii）与第二电极接触的第二表面。 第一表面限定第一表面区域，第二表面限定第二表面区域。 第一表面积大于第二表面积。

公开(公告)号：US10784167B2

公开(公告)日：2020-09-22

申请号：US16230505

申请日：2018-12-21

Applicant: Marvell World Trade Ltd.

Inventor： Runzi Chang ,  Chuan-Cheng Cheng

IPC: H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/764 ,  H01L27/12 ,  H01L21/28

Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.