- Patent Title: Paired value comparison for redundant multi-threading operations
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Application No.: US15231251Application Date: 2016-08-08
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Publication No.: US10042687B2Publication Date: 2018-08-07
- Inventor: Daniel I. Lowell , Manish Gupta
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F11/14
- IPC: G06F11/14 ; G06F11/07 ; G06F9/30 ; G06F9/38

Abstract:
Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action.
Public/Granted literature
- US20180039531A1 PAIRED VALUE COMPARISON FOR REDUNDANT MULTI-THREADING OPERATIONS Public/Granted day:2018-02-08
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