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    SCHEDULING USING COLLAPSED OPERATIONS
    1.
    发明申请
    SCHEDULING USING COLLAPSED OPERATIONS 有权

    公开(公告)号：US20250165284A1

    公开(公告)日：2025-05-22

    申请号：US18518204

    申请日：2023-11-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Travis Boraten ,  Heather Lynn Hanson ,  Yasuko Eckert ,  Onur Kayiran

    IPC: G06F9/48

    Abstract: A method for collapsing operations into super operations in a computing system includes dispatching a super operation corresponding to a collapsible sequence of operations to a scheduler, performing a lookup in a super operation table for the collapsible sequence of operations in response to the super operation being picked from the scheduler, and multi-pumping the collapsible sequence of operations to a pipe operationally coupled to the scheduler. For example, the multi-pumped collapsible sequence of operations may then be sequentially executed by an execution unit. The collapsible sequence of operations may be identified as collapsible according to a set of rules.

    PREFETCHING USING A DIRECT MEMORY ACCESS ENGINE
    2.
    发明申请
    PREFETCHING USING A DIRECT MEMORY ACCESS ENGINE 有权

    公开(公告)号：US20250156329A1

    公开(公告)日：2025-05-15

    申请号：US18388940

    申请日：2023-11-13

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Vydhyanathan Kalyanasundharam ,  Christopher J. Brennan ,  Joseph L. Greathouse ,  Mark Fowler

    IPC: G06F12/0862 ,  G06F13/28

    Abstract: A processing system includes one or more DMA engines that load data from memory or another cache location without storing the data after loading it. As the data propagates past caches located between the memory or other cache location that stores the requested data (“intermediate caches”), the data is selectively copied to the intermediate caches based on a cache replacement policy. Rather than the DMA engine manually storing the data into the intermediate caches, the cache replacement policies of the intermediate caches determine whether the data is copied into each respective cache and a replacement priority of the data. By bypassing storing the data, the DMA engine effectuates prefetching to the intermediate caches without expending unnecessary bandwidth or searching for a memory location to store the data, thus reducing latency and saving energy.

    Memory controller with enhanced low-power state
    4.
    发明授权
    Memory controller with enhanced low-power state 有权

    公开(公告)号：US12299297B2

    公开(公告)日：2025-05-13

    申请号：US18216109

    申请日：2023-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Jean J. Chittilappilly ,  Tahsin Askar ,  James R. Magro

    IPC: G06F3/06

    Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

    CHIP PACKAGE WITH ACTIVE SILICON BRIDGE
    6.
    发明申请
    CHIP PACKAGE WITH ACTIVE SILICON BRIDGE 有权

    公开(公告)号：US20250149525A1

    公开(公告)日：2025-05-08

    申请号：US18615918

    申请日：2024-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Deepak Vasant KULKARNI ,  Alan D. SMITH ,  Raja SWAMINATHAN

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H10B80/00

    Abstract: Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.

    PRE-CONDITIONING OF BLOCK-BASED COMPRESSION BLOCKS FOR LOSSLESS CODECS
    7.
    发明申请
    PRE-CONDITIONING OF BLOCK-BASED COMPRESSION BLOCKS FOR LOSSLESS CODECS 有权

    公开(公告)号：US20250148645A1

    公开(公告)日：2025-05-08

    申请号：US18386655

    申请日：2023-11-03

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Navin Patel ,  Shashank Ranjan

    IPC: G06T9/00

    Abstract: A processing system preconditions block-compressed texture blocks by separately streaming color components and index components for lossless compression. The processing system preconditions the color components for linear compression, such that color component data for adjacent compressed blocks in a row are further compressed using lossless compression. Lossless compression is performed for color components spanning multiple rows to leverage patterns in color components that extend vertically across a frame. The processing system further divides input color component and index component data into pages of memory (e.g., 64 kB pages), such that each page can be independently losslessly compressed and decompressed. The processing system applies delta encoding to color component data so that a single instance of color data and differences from the stored color data are stored for each page.

    Method and apparatus for managing memory
    8.
    发明授权
    Method and apparatus for managing memory 有权

    公开(公告)号：US12293092B2

    公开(公告)日：2025-05-06

    申请号：US18083306

    申请日：2022-12-16

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Lu Lu ,  Anthony Asaro ,  Yinan Jiang

    IPC: G06F3/06

    Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

    MULTIPLEXED BUS STREAK MANAGEMENT
    9.
    发明申请
    MULTIPLEXED BUS STREAK MANAGEMENT 有权

    公开(公告)号：US20250139022A1

    公开(公告)日：2025-05-01

    申请号：US18891278

    申请日：2024-09-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kedarnath Balakrishnan ,  James R. Magro

    IPC: G06F13/16 ,  G06F13/40

    Abstract: A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.

    Security Framework for Virtual Machines
    10.
    发明申请
    Security Framework for Virtual Machines 有权

    公开(公告)号：US20250130844A1

    公开(公告)日：2025-04-24

    申请号：US18926095

    申请日：2024-10-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Reshma Lal ,  David A. Kaplan ,  Jelena Ilic

    IPC: G06F9/455

    Abstract: A security framework for virtual machines is described. In one or more implementations, a hardware platform comprises physical computer hardware, the physical computer hardware including one or more processing units and one or more memories. The system also includes a virtual machine monitor configured to virtualize the physical computer hardware of the hardware platform to instantiate a plurality of framework-secure virtual machines. Further, the system includes a root framework-secure virtual machine instantiated by the virtual machine monitor. In accordance with the described techniques, the root framework-secure virtual machine is configured to control access to the hardware platform by the framework-secure virtual machines instantiated by the virtual machine monitor.

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