Invention Grant
- Patent Title: Patterned layer design for group III nitride layer growth
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Application No.: US15797263Application Date: 2017-10-30
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Publication No.: US10050175B2Publication Date: 2018-08-14
- Inventor: Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
- Applicant: Sensor Electronic Technology, Inc.
- Applicant Address: US SC Columbia
- Assignee: Sensor Electronic Technology, Inc.
- Current Assignee: Sensor Electronic Technology, Inc.
- Current Assignee Address: US SC Columbia
- Agency: LaBatt, LLC
- Main IPC: H01L27/15
- IPC: H01L27/15 ; H01L31/072 ; H01L33/06 ; H01L21/02 ; H01L29/778 ; H01L33/12 ; H01L33/24 ; H01L33/32 ; H01L29/20 ; H01L29/51 ; H01L33/22

Abstract:
A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
Public/Granted literature
- US20180047870A1 Patterned Layer Design for Group III Nitride Layer Growth Public/Granted day:2018-02-15
Information query
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