An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.