Invention Grant
- Patent Title: P-FET with strained silicon-germanium channel
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Application No.: US15402265Application Date: 2017-01-10
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Publication No.: US10079181B2Publication Date: 2018-09-18
- Inventor: Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Ghavam G. Shahidi
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent L. Jeffrey Kelly
- Main IPC: H01L21/225
- IPC: H01L21/225 ; H01L21/8234 ; H01L21/8238 ; H01L29/78 ; H01L29/66 ; H01L21/02 ; H01L21/308

Abstract:
A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
Public/Granted literature
- US20170125303A1 P-FET WITH STRAINED SILICON-GERMANIUM CHANNEL Public/Granted day:2017-05-04
Information query
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