公开(公告)号：US12279452B2

公开(公告)日：2025-04-15

申请号：US17551309

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li

IPC: H10D30/69 ,  H01L23/528 ,  H10D30/01 ,  H10D30/67 ,  H10D64/01 ,  H10D64/23 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source/drain element of the first transistor to the first interconnect structure. The second contact connects a first source/drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

公开(公告)号：US12208386B2

公开(公告)日：2025-01-28

申请号：US18234004

申请日：2023-08-15

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Kangguo Cheng ,  Donald Canaperi ,  Shawn Peter Fetterolf

IPC: B01L3/00 ,  B82B1/00 ,  B82B3/00

Abstract: 3D nanochannel interleaved devices for molecular manipulation are provided. In one aspect, a method of forming a device includes: forming a pattern on a substrate of alternating mandrels and spacers alongside the mandrels; selectively removing the mandrels from a front portion of the pattern forming gaps between the spacers; selectively removing the spacers from a back portion of the pattern forming gaps between the mandrels; filling i) the gaps between the spacers with a conductor to form first electrodes and ii) the gaps between the mandrels with the conductor to form second electrodes; and etching the mandrels and the spacers in a central portion of the pattern to form a channel (e.g., a nanochannel) between the first electrodes and the second electrodes, wherein the first electrodes and the second electrodes are offset from one another across the channel, i.e., interleaved. A device formed by the method is also provided.

公开(公告)号：US12191208B2

公开(公告)日：2025-01-07

申请号：US17482573

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

Abstract: A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.

公开(公告)号：US12148663B2

公开(公告)日：2024-11-19

申请号：US17522543

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Kisik Choi ,  Kangguo Cheng

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

Abstract: Tiered-profile contacts for semiconductor devices and techniques for formation thereof are provided In one aspect, a method for forming tiered-profile contacts to a semiconductor device includes: depositing a first oxide layer over the semiconductor device; depositing a second oxide layer on the first oxide layer; patterning contact trenches through the first/second oxide layer down to the semiconductor device; isotropically etching a top portion of the contact trenches selective to a bottom portion of the contact trenches based on the second oxide layer having a greater etch rate than the first oxide layer to make the top portion of the contact trenches wider than the bottom portion; and filling the contact trenches with a contact metal(s) to form the tiered-profile contacts. Other methods to form tiered-profile contacts using sacrificial spacers as well as structures including the present tiered-profile contacts are also provided.

公开(公告)号：US12112782B2

公开(公告)日：2024-10-08

申请号：US17469350

申请日：2021-09-08

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Karthik Yogendra ,  Dimitri Houssameddine ,  Kangguo Cheng ,  Ruilong Xie

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

公开(公告)号：US12107147B2

公开(公告)日：2024-10-01

申请号：US17551686

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Kangguo Cheng ,  Su Chen Fan ,  Miaomiao Wang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

公开(公告)号：US12106969B2

公开(公告)日：2024-10-01

申请号：US17205037

申请日：2021-03-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Mukta Ghate Farooq ,  Julien Frougier ,  Takeshi Nogami ,  Roy R. Yu ,  Kangguo Cheng

IPC: H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/30625 ,  H01L21/76224 ,  H01L21/76816 ,  H01L23/5286

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

公开(公告)号：US20240324475A1

公开(公告)日：2024-09-26

申请号：US18188729

申请日：2023-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Arthur Roy Gasasira ,  LOUIS ZUOGUANG LIU ,  Amlan Majumdar

IPC: H10N70/20 ,  G11C13/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  G11C13/0004 ,  G11C13/0069 ,  H10N70/023 ,  H10N70/063 ,  H10N70/066 ,  H10N70/841 ,  H10N70/8613

Abstract: The density of deuterium or hydrogen within phase change material (PCM) of a PCM memory cell reduces the active defects in the amorphous phase of the PCM by passivating dangling bonds, which results in the PCM becoming easier to nucleate during the SET process of the PCM memory cell. Resultingly, the addition of deuterium or hydrogen within the PCM relatively increases the SET programming voltage window of the PCM memory cell compared with a similar PCM cell without.

公开(公告)号：US12087770B2

公开(公告)日：2024-09-10

申请号：US17394701

申请日：2021-08-05

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Heng Wu ,  Chen Zhang ,  Kangguo Cheng

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0688 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

公开(公告)号：US20240242012A1

公开(公告)日：2024-07-18

申请号：US18097185

申请日：2023-01-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Mukta Ghate Farooq ,  Albert M. Chu ,  Julien Frougier ,  Kangguo Cheng ,  Chanro Park

IPC: G06F30/3308 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/3308 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: An integrated circuit has a frontside and a backside and includes a first CMOS cell of complementary metal oxide semiconductor (CMOS) devices. A first row of gate cuts and a second row of gate cuts bound the first CMOS cell. A gate is associated with at least one of the devices in the first CMOS cell. A first signal line is at the frontside of the integrated circuit. A signal connection is provided from the first signal line to the backside of the integrated circuit. A local interconnect is provided at the backside of the integrated circuit from the signal connection to the gate.