Invention Grant
- Patent Title: Vertical semiconductor structure
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Application No.: US15365335Application Date: 2016-11-30
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Publication No.: US10177218B2Publication Date: 2019-01-08
- Inventor: Frédéric Lanois , Alexei Ankoudinov , Vladimir Rodov
- Applicant: STMicroelectronics (Tours) SAS
- Applicant Address: FR Tours
- Assignee: STIMICROELECTRONICS (TOURS) SAS
- Current Assignee: STIMICROELECTRONICS (TOURS) SAS
- Current Assignee Address: FR Tours
- Agency: Slater Matsil, LLP
- Priority: FR1653369 20160415; FR1653371 20160415
- Main IPC: H02M3/158
- IPC: H02M3/158 ; H01L29/06 ; H01L29/861 ; H01L29/10 ; H01L29/423 ; H01L29/78 ; H01L27/06 ; H01L27/092

Abstract:
A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.
Public/Granted literature
- US20170301752A1 Vertical Semiconductor Structure Public/Granted day:2017-10-19
Information query
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