Invention Grant
- Patent Title: Semiconductor heterostructure with stress management
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Application No.: US15660191Application Date: 2017-07-26
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Publication No.: US10199531B2Publication Date: 2019-02-05
- Inventor: Daniel Billingsley , Robert M. Kennedy , Wenhong Sun , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
- Applicant: Sensor Electronic Technology, Inc.
- Applicant Address: US SC Columbia
- Assignee: Sensor Electronic Technology, Inc.
- Current Assignee: Sensor Electronic Technology, Inc.
- Current Assignee Address: US SC Columbia
- Agency: LaBatt, LLC
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L33/00 ; H01L33/32 ; H01L33/12 ; H01L33/20 ; H01L33/24 ; H01L21/02 ; H01L33/06
Abstract:
A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
Public/Granted literature
- US20170338371A1 Semiconductor Heterostructure with Stress Management Public/Granted day:2017-11-23
Information query
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