Invention Grant
- Patent Title: Wafer tap domain die channel circuitry with separate die clocks
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Application No.: US16026721Application Date: 2018-07-03
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Publication No.: US10209305B2Publication Date: 2019-02-19
- Inventor: Lee D. Whetsel
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317 ; G01R31/3185 ; G01R31/3187 ; G01R31/28

Abstract:
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
Public/Granted literature
- US20180321307A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE Public/Granted day:2018-11-08
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