Invention Grant
- Patent Title: Synchronous input / output hardware acknowledgement of write completions
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Application No.: US15190250Application Date: 2016-06-23
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Publication No.: US10229084B2Publication Date: 2019-03-12
- Inventor: Scott A. Brewer , David F. Craddock , Matthew J. Kalos , Matthias Klein , Eric N. Lais
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Steven Chiu
- Main IPC: G06F13/36
- IPC: G06F13/36 ; G06F13/42 ; G06F13/40 ; G06F13/28

Abstract:
A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.
Public/Granted literature
- US20170371828A1 SYNCHRONOUS INPUT / OUTPUT HARDWARE ACKNOWLEDGEMENT OF WRITE COMPLETIONS Public/Granted day:2017-12-28
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