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    TECHNIQUE TO HANDLE INSUFFICIENT ON-CHIP MEMORY CAPACITY IN DECOMPRESSORS
    1.
    发明申请
    TECHNIQUE TO HANDLE INSUFFICIENT ON-CHIP MEMORY CAPACITY IN DECOMPRESSORS 有权

    公开(公告)号：US20250004638A1

    公开(公告)日：2025-01-02

    申请号：US18217480

    申请日：2023-06-30

    Applicant: International Business Machines Corporation

    Inventor： Bulent Abali ,  Matthias Klein ,  Ashutosh Mishra ,  Girish Gopala Kurup

    IPC: G06F3/06

    Abstract: A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.

    SYSTEM FOR COLLABORATIVE HARDWARE RTL LOGIC TIMING DEBUG IN INTEGRATED CIRCUIT DESIGNS
    5.
    发明公开
    SYSTEM FOR COLLABORATIVE HARDWARE RTL LOGIC TIMING DEBUG IN INTEGRATED CIRCUIT DESIGNS 审中-公开

    公开(公告)号：US20230214564A1

    公开(公告)日：2023-07-06

    申请号：US17567598

    申请日：2022-01-03

    Applicant: International Business Machines Corporation

    Inventor： Arun Joseph ,  Wolfgang Roesner ,  Shashidhar Reddy ,  SAMPATH GOUD BADDAM ,  Anthony Saporito ,  Matthias Klein

    IPC: G06F30/327

    CPC classification number: G06F30/327 ,  G06F2119/12

    Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION
    9.
    发明申请
    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION 有权

    公开(公告)号：US20210311891A1

    公开(公告)日：2021-10-07

    申请号：US17354302

    申请日：2021-06-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Peter Dana Driever ,  Brenton Belmar

    IPC: G06F13/16 ,  G06F9/30

    Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

    Instant quiescing of an accelerator
    10.
    发明授权
    Instant quiescing of an accelerator 有权

    公开(公告)号：US11119928B2

    公开(公告)日：2021-09-14

    申请号：US16286861

    申请日：2019-02-27

    Applicant: International Business Machines Corporation

    Inventor： Matthias Klein ,  Ashutosh Misra ,  Girish Gopala Kurup

    IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/28 ,  G06F9/38

    Abstract: A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.

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