Invention Grant
- Patent Title: Conductive paths through dielectric with a high aspect ratio for semiconductor devices
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Application No.: US15427984Application Date: 2017-02-08
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Publication No.: US10229858B2Publication Date: 2019-03-12
- Inventor: Thorsten Meyer , Andreas Wolter
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L21/56 ; H01L23/498 ; H01L23/538 ; H01L21/683 ; H01L23/522 ; H01L25/18 ; H01L23/525

Abstract:
Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector is over each filled via.
Public/Granted literature
- US20170148698A1 CONDUCTIVE PATHS THROUGH DIELECTRIC WITH A HIGH ASPECT RATIO FOR SEMICONDUCTOR DEVICES Public/Granted day:2017-05-25
Information query
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