公开(公告)号：US10896780B2

公开(公告)日：2021-01-19

申请号：US15910820

申请日：2018-03-02

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC: H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F27/28 ,  H01L23/532 ,  H03B5/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/768

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

公开(公告)号：US10431545B2

公开(公告)日：2019-10-01

申请号：US15637641

申请日：2017-06-29

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Laurent Millou

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  G11C16/18

Abstract: A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

公开(公告)号：US10228725B2

公开(公告)日：2019-03-12

申请号：US15282633

申请日：2016-09-30

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

IPC: A44C5/00 ,  A44C5/02 ,  A44C5/10 ,  A45F5/00 ,  A61B5/00 ,  A61B5/11 ,  G06F1/16 ,  A61B5/021 ,  A61B5/024 ,  G04B37/14 ,  G04B47/00 ,  A61B5/0205 ,  H04B1/3827

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

公开(公告)号：US20210104359A1

公开(公告)日：2021-04-08

申请号：US17122351

申请日：2020-12-15

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC: H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F27/28

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

公开(公告)号：US10816742B2

公开(公告)日：2020-10-27

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/30 ,  G02B6/12 ,  G02B6/43

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10535578B2

公开(公告)日：2020-01-14

申请号：US15719653

申请日：2017-09-29

Applicant: Intel IP Corporation

Inventor： Reinhard Mahnkopf ,  Andreas Wolter ,  Sonja Koller

IPC: H01L21/48 ,  H01L23/367 ,  H01L27/02 ,  H01L23/498 ,  H01L21/762 ,  H01L27/12 ,  H01L23/373 ,  H01L25/065 ,  H01L21/84

Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

公开(公告)号：US10411000B2

公开(公告)日：2019-09-10

申请号：US15087477

申请日：2016-03-31

Applicant: Intel IP Corporation

Inventor： Marc Stephan Dittes ,  Sven Albers ,  Christian Georg Geissler ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Thomas Wagner ,  Richard Patten

IPC: F21V15/00 ,  H01L25/16 ,  H01L23/31

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

公开(公告)号：US10373844B2

公开(公告)日：2019-08-06

申请号：US15590890

申请日：2017-05-09

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US20170345678A1

公开(公告)日：2017-11-30

申请号：US15590890

申请日：2017-05-09

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US20170062306A1

公开(公告)日：2017-03-02

申请号：US14839510

申请日：2015-08-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Alexandra Atzesdorfer ,  Sonja Koller

IPC: H01L23/427 ,  H01L23/373

CPC classification number: H01L23/3737 ,  G06F1/203 ,  G06F2200/201 ,  H01L23/373 ,  H01L23/427 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及一种用于半导体器件的冷却器。 半导体器件可以电耦合到电源。 当设备使用期间电源向设备供电时，设备可能会产生热量。 冷却器可以联接到装置的一个或多个表面。 冷却器可以包括用于从环境空气中吸附水的亲水材料。 在设备运行期间，冷却器可以通过将热量从设备传导到冷却器来冷却设备。 冷却器可以包括在使用装置期间蒸发的水以增加冷却器的冷却能力。 当设备未在较低功率水平下操作或操作时，冷却器可能会在空气中从潮湿的水中充电。 可以描述和/或要求保护其他实施例。