Invention Grant
- Patent Title: Load balancing systems, devices, and methods
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Application No.: US15468835Application Date: 2017-03-24
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Publication No.: US10243856B2Publication Date: 2019-03-26
- Inventor: Patrick L. Connor , Parthasarathy Sarangam
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H04L12/803
- IPC: H04L12/803 ; H04L12/26 ; H04L12/721 ; H04L12/707 ; H04L12/841 ; H04L29/14 ; H04L12/933

Abstract:
Embodiments regard load balancing data on one or more network ports. A device may include processing circuitry, the processing circuitry to transmit a first packet of a first series of packets to a destination device via a first port, determine a time gap between a first packet and a second packet of the first series of packets, and in response to a determination that the time gap is greater than a time threshold, transmit the second packet to the destination device via a second port.
Public/Granted literature
- US20180278530A1 LOAD BALANCING SYSTEMS, DEVICES, AND METHODS Public/Granted day:2018-09-27
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