Invention Grant
- Patent Title: Ge nano wire transistor with GaAs as the sacrificial layer
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Application No.: US15576666Application Date: 2015-06-27
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Publication No.: US10249740B2Publication Date: 2019-04-02
- Inventor: Willy Rachmady , Matthew V. Metz , Van H. Le , Jack T. Kavalieros , Sanaz K. Gardner
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/038190 WO 20150627
- International Announcement: WO2017/003407 WO 20170105
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/423 ; H01L29/775 ; H01L29/06 ; H01L29/16 ; H01L27/092 ; H01L29/08 ; H01L29/267 ; H01L29/78 ; H01L21/02 ; H01L21/306 ; H01L29/20

Abstract:
An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
Public/Granted literature
- US20180138289A1 GE NANO WIRE TRANSISTOR WITH GAAS AS THE SACRIFICIAL LAYER Public/Granted day:2018-05-17
Information query
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