公开(公告)号：US20250107147A1

公开(公告)日：2025-03-27

申请号：US18476248

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar E. Avci ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Jack T. Kavalieros ,  Chia-Ching Lin ,  Matthew V. Metz ,  Wouter Mortelmans ,  Carl Hugo Naylor ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carly Rogan ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Andrey Vyatskikh

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

公开(公告)号：US12183831B2

公开(公告)日：2024-12-31

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Miriam R. Reshotko ,  Shriram Shivaraman ,  Li Huey Tan ,  Tristan A. Tronic ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20240355682A1

公开(公告)日：2024-10-24

申请号：US18761493

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US12068206B2

公开(公告)日：2024-08-20

申请号：US17030449

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US11929435B2

公开(公告)日：2024-03-12

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US20230420562A1

公开(公告)日：2023-12-28

申请号：US17809329

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Munzarin F. Qayyum ,  Nicole K. Thomas ,  Rohit Galatage ,  Patrick Morrow ,  Jami A. Wiedemer ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66795

Abstract: Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.

公开(公告)号：US20230420507A1

公开(公告)日：2023-12-28

申请号：US17847559

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Anand Murthy ,  Jack T. Kavalieros ,  Rajat K. Paul ,  Susmita Ghose ,  Seung Hoon Sung

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: Semiconductor devices on a substrate with an alternative crystallographic surface orientation. Example devices includes gate-all-around (e.g., nanoribbon and nanosheet) and forksheet transistors. In an example, a substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating silicon germanium (SiGe) or germanium tin (GeSn) and silicon (Si) semiconductor layers. P-channel transistors may be formed using SiGe or GeSn nanoribbons while n-channel transistors are formed from Si nanoribbons. The crystallographic surface orientation of the SiGe or GeSn nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the SiGe or GeSn nanoribbons and improved device performance.